Characterizing Logical Masking Of Transient Faults At The Microarchitectural And Architectural Levels

In this work, the e#ects of transient faults on high performance microprocessors is explored. To perform a thorough exploration, a highly detailed RTL model of a modern, deeply pipelined, out-of-order microprocessor implementing the Alpha ISA was created. Using this model, the e#ects of manipulating individual state elements such as pipeline latches and RAM cells can be observed by comparing the results against that of a reference simulation. Using statistical fault injection into our...