Group: BYU CHREC B1 2009 - library 83 articles Export

	Iterative Modulo Scheduling [My Copy] The International Journal of Parallel Processing, Vol. 24, No. 1. (February 1996) by B. Ramakrishna Rau posted to scheduling by adamarnesen to the group BYU CHREC B1 2009 on 2009-12-08 18:39:08 as
	Vista Architect: System Level Design Solution for Performance and Power [My Copy] (August 2009) posted to tlm by adamarnesen to the group BYU CHREC B1 2009 on 2009-09-28 19:11:58 as
	Iterative modulo scheduling: an algorithm for software pipelining loops [My Copy] In MICRO 27: Proceedings of the 27th annual international symposium on Microarchitecture (1994), pp. 63-74. by B. Ramakrishna Rau posted to algorithm by jcarroll to the group BYU CHREC B1 2009 on 2009-08-14 15:11:30 as along with 3 people and 2 groups iammealva greenShell visit0r CompArch Compilers
	SpiritEd: A Register Specification System integrating IP-XACT and Adobe FrameMaker [My Copy] (July 2009) by Jan Langer, Vasco Jerinic, Ulrich Heinkel, Frank Dresig posted to ip-xact by jcarroll to the group BYU CHREC B1 2009 on 2009-07-18 00:06:55 as
	Interface Theories for Component-Based Design [My Copy] Embedded Software (2001), pp. 148-165. by Luca de Alfaro, Thomas Henzinger posted to automata by adamarnesen to the group BYU CHREC B1 2009 on 2009-07-14 22:19:38 as
	Object-oriented high-level modeling of system components for the generation of VHDL code [My Copy] In EURO-DAC '95/EURO-VHDL '95: Proceedings of the conference on European design automation (1995), pp. 436-441. by Karlheinz Agsteiner, Dieter Monjau, Sören Schulze posted to vhdl-code-generation by jcarroll to the group BYU CHREC B1 2009 on 2009-06-19 17:47:53 as
	VHDL code generation framework in Ptolemy II [My Copy] (February 2007) by Vinayak Nagpal, Terry Filiba, Man K. Leung posted to ptolomy vhdl-code-generation by jcarroll to the group BYU CHREC B1 2009 on 2009-06-15 17:06:01 as
	VHDL Code Generation in the Ptolemy II Environment [My Copy] No. UCB/EECS-2008-140. (Oct 2008) by Man K. Leung, Terry E. Filiba, Vinayak Nagpal posted to ptolomy vhdl-code-generation by jcarroll to the group BYU CHREC B1 2009 on 2009-06-15 17:05:17 as
	Taming heterogeneity - the Ptolemy approach [My Copy] Proceedings of the IEEE, Vol. 91, No. 1. (2003), pp. 127-144. by J. Eker, J. W. Janneck, E. A. Lee, et al.Jie Liu, Xiaojun Liu, J. Ludvig, S. Neuendorffer, S. Sachs, Yuhong Xiong posted to ptolemy by jcarroll to the group BYU CHREC B1 2009 on 2009-06-15 16:55:07 as along with 2 people NickGasson berndi
	Overview of the Ptolemy Project [My Copy] (2 July 2003) by Christopher Hylands, Edward Lee, Jie Liu, et al.Xiaojun Liu, Stephen Neuendorffer, Yuhong Xiong, Yang Zhao, Haiyang Zheng edited by Edward A. Lee posted to ptolemy by jcarroll to the group BYU CHREC B1 2009 on 2009-06-15 16:54:35 as
	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs [My Copy] Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on In Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on (2003), pp. 284-285. by A. Jones, P. Banerjee posted to core_reuse synthesis by derrickgw to the group BYU CHREC B1 2009 on 2009-06-12 17:58:42 as
	SpecC: Specification Language and Methodology [My Copy] (01 March 2000) by Daniel D. Gajski, Jianwen Zhu, Rainer Domer, Andreas Gerstlauer, Shuqing Zhao posted to fsm by adamarnesen to the group BYU CHREC B1 2009 on 2009-06-03 16:29:33 as
	Using statecharts for hardware description and synthesis [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 8, No. 7. (1989), pp. 798-807. by D. Drusinsky, D. Harel posted to fsm by adamarnesen to the group BYU CHREC B1 2009 on 2009-06-03 16:23:03 as
	Modeling hierarchical combinational circuits [My Copy] In ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design (1993), pp. 612-617. by Jerry R. Burch, David Dill, Elizabeth Wolf, Giovanni de Micheli posted to no-tag by adamarnesen to the group BYU CHREC B1 2009 on 2009-05-28 22:21:34 as
	Semantic foundations for heterogeneous systems [My Copy] (2004) by Roberto Passerone posted to agent-algebras by jcarroll to the group BYU CHREC B1 2009 on 2009-05-20 23:39:09 as
	High-Level specification and automatic generation of IP interface monitors [My Copy] In DAC '02: Proceedings of the 39th conference on Design automation (2002), pp. 129-134. by Marcio T. Oliveira, Alan J. Hu posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-05-16 22:41:49 as
	Synthesis of digital automata. [My Copy] (1969) by V. G. Lazarev, A. D. Zakrevskii posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-05-16 18:53:36 as
	Introduction to automata theory, languages, and computation [My Copy] (2007) by John E. Hopcroft, Rajeev Motwani, Jeffrey D. Ullman posted to automata by jcarroll to the group BYU CHREC B1 2009 on 2009-05-08 00:08:50 as
	Distributed and Parallel Embedded Systems (IFIP International Federation for Information Processing) [My Copy] (30 September 1999) posted to regex by adamarnesen to the group BYU CHREC B1 2009 on 2009-05-07 20:26:25 as
	The compilation of regular expressions into integrated circuits [My Copy] Foundations of Computer Science, 1980., 21st Annual Symposium on In Foundations of Computer Science, 1980., 21st Annual Symposium on (1980), pp. 260-269. by Robert W. Floyd, Jeffrey D. Ullman posted to regex by adamarnesen to the group BYU CHREC B1 2009 on 2009-05-06 17:58:23 as
	High-level synthesis: an essential ingredient for designing complex ASICs [My Copy] Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on In Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on (2004), pp. 775-782. by Arvind, R. S. Nikhil, D. L. Rosenband, N. Dave posted to high-level-synthesis by jcarroll to the group BYU CHREC B1 2009 on 2009-05-06 02:54:13 as
	Structured Component Composition Frameworks for Embedded System Design [My Copy] In HiPC '02: Proceedings of the 9th International Conference on High Performance Computing (2002), pp. 663-678. by Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta posted to abstraction productivity reuse by jcarroll to the group BYU CHREC B1 2009 on 2009-05-06 02:47:03 as
	Synthesis of Interface Automata [My Copy] Automated Technology for Verification and Analysis (2005), pp. 338-353. by Purandar Bhaduri posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-05-04 19:54:01 as along with 2 people lmorel Scis0000002
	MetaRTL: raising the abstraction level of RTL design [My Copy] In DATE '01: Proceedings of the conference on Design, automation and test in Europe (2001), pp. 71-76. by J. Zhu posted to other by adamarnesen to the group BYU CHREC B1 2009 on 2009-04-29 21:22:41 as
	A Multi-Layered XML Schema and Design Tool for Reusing and Integrating FPGA IP [My Copy] In Field Programmable Logic (2009) by Adam Arnesen, Nathaniel Rollins, Michael Wirthlin posted to no-tag by adamarnesen to the group BYU CHREC B1 2009 on 2009-04-29 21:01:53 as
	OpenCores HDL modeling guidelines: This document describes the OpenCores HDL modelling guidelines with some examples [My Copy] (9 April 2009) by Opencores Community, Michael Unneback, Marko Mlinar, Damjan Lampret, Jamil Khatib, Yair Amitay posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-04-28 15:35:27 as
	API Guidelines Addendum [My Copy] (2006) by Kosta Ilic, Ben Weidman posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-03-07 22:25:59 as
	LabVIEW FPGA API Design Guidelines [My Copy] (30 October 2006) by Kosta Ilic, Ben Weidman posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-03-07 22:23:28 as
	Systematic transaction level modeling of embedded systems with SystemC [My Copy] Design, Automation and Test in Europe, 2005. Proceedings (2005) by W. Klingauf posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-03-07 22:10:29 as
	A system for compiling and debugging structured data processing controllers [My Copy] In EURO-DAC '96/EURO-VHDL '96: Proceedings of the conference on European design automation (1996), pp. 86-91. by A. Seawright, J. Buck, U. Holtmann, W. Meyer, B. Pangrle, R. Verbrugghe posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-20 17:25:03 as
	Grammar-based specification and synthesis for synchronous digital hardware design [My Copy] (1994) by Andrew Seawright posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-20 17:20:06 as
	An XML Schema for Representing Reuable IP Cores for Reconfigurable Computing [My Copy] In Proceedings of the National Aerospace and Electronics Conference (NAECON 2008) (July 2008) by Nathaniel Rollins, Adam Arnesen, Michael Wirthlin posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-13 00:51:21 as
	Automation of IP Core Interface Generation for Reconfigurable Computing [My Copy] Field Programmable Logic and Applications, 2006. FPL '06. International Conference on In Field Programmable Logic and Applications, 2006. FPL '06. International Conference on (2006), pp. 1-6. by Zhi Guo, A. Mitra, W. Najjar posted to other by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:52:51 as
	Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol TM [My Copy] by W. D. Weber, I. Sonics posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:46:43 as
	Integration architecture for system-on-a-chip design [My Copy] Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998 In Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998 (1998), pp. 85-88. by D. Wingard, A. Kurosawa posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:42:59 as
	Towards evolvable IP cores for FPGAs [My Copy] Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on In Evolvable Hardware, 2003. Proceedings. NASA/DoD Conference on (2003), pp. 145-154. by L. Sekanina posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:41:36 as
	Application of UML for hardware design based on design process model [My Copy] In ASP-DAC '04: Proceedings of the 2004 conference on Asia South Pacific design automation (2004), pp. 244-249. by Robertas Damasevicius, Vytautas Stuikys posted to other by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:38:50 as
	An object-oriented model for specification, prototyping, implementation and reuse [My Copy] In DATE '98: Proceedings of the conference on Design, automation and test in Europe (1998), pp. 303-311. by J. Böttger, K. Agsteiner, D. Monjau, S. Schulze posted to other by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:37:56 as
	Transaction level modeling: an overview [My Copy] In CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (2003), pp. 19-24. by Lukai Cai, Daniel Gajski posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:37:03 as along with 2 people Joshd hannibal_07
	Introduction to Hardware Abstraction Layers for SoC [My Copy] In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe (2003) by Sungjoo Yoo, Ahmed A. Jerraya posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:35:59 as
	When FPGAs are better at floating-point than microprocessors [My Copy] In FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays (2008), pp. 260-260. by Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-02-12 23:34:13 as along with 1 person and 1 group mmuecke Reconfigurable Computing
	OPENCORES.ORG [My Copy] posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-26 23:42:24 as
	Using LabVIEW FPGA with the Xilinx SPARTAN-3E XUP Starter Kit - National Instruments [My Copy] posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-26 23:18:45 as
	Protocol Transducer Synthesis using Divide and Conquer approach [My Copy] In ASP-DAC '07: Proceedings of the 2007 conference on Asia South Pacific design automation (2007), pp. 280-285. by S. Watanabe, K. Seto, Y. Ishikawa, S. Komatsu, M. Fujita posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-21 20:50:54 as
	Generation of processor interface for SoC using standard communication protocol [My Copy] Computers and Digital Techniques, IEE Proceedings - In Computers and Digital Techniques, IEE Proceedings -, Vol. 151, No. 5. (2004), pp. 367-376. by G. Cyr, G. Bois, M. Aboulhamid posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-21 20:33:32 as
	Interface Synthesis from Protocol Specification [My Copy] Center for Embedded Computer Systems (2002) by D. Shin, D. Gajski posted to timing-diagram by jcarroll to the group BYU CHREC B1 2009 on 2009-01-19 23:11:35 as along with 1 person adamarnesen
	Interfacing Incompatible Protocols Using Interface Process Generation [My Copy] Design Automation, 1995. DAC '95. 32nd Conference on In Design Automation, 1995. DAC '95. 32nd Conference on (1995), pp. 468-473. by Sanjiv posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-19 22:58:09 as
	Designing systems-on-chip using cores [My Copy] In DAC '00: Proceedings of the 37th conference on Design automation (2000), pp. 420-425. by Reinaldo A. Bergamaschi, William R. Lee posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-19 22:34:28 as
	An interface protocol component modeling language [My Copy] ASIC/SOC Conference, 2002. 15th Annual IEEE International (2002), pp. 456-460. by Chang-Yul Yun, Kyoung-Son Jhang posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-17 23:48:56 as
	Bluespec System Verilog: efficient, correct RTL from high level specifications [My Copy] Formal Methods and Models for Co-Design, 2004. MEMOCODE '04. Proceedings. Second ACM and IEEE International Conference on (June 2004), pp. 69-70. by R. Nikhil posted to no-tag by jcarroll to the group BYU CHREC B1 2009 on 2009-01-17 22:34:46 as

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fsm	15
regex	7
other	4
vhdl-code-generation	3
high-level-synthesis	2
ptolomy	2
automata	2
ptolemy	2
synthesis	1
tlm	1
agent-algebras	1
abstraction	1
reuse	1
core_reuse	1
timing-diagram	1
ip-xact	1
algorithm	1
productivity	1
scheduling	1

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