Thu, 21 Aug 2008 10:09:11 BST CiteULike: Tag cache http://www.citeulike.org/tag/cache CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/yuhuang/article/2150365 <i>(2007), pp. 239-250.</i> Achieving Flexible Cache Consistency for Pervasive Internet Access Yu Huang Jiannong Cao Zhijun Wang Beihong Jin Yulin Feng doi:10.1109/PERCOM.2007.6 (2007), pp. 239-250. 2007-12-20T07:49:46-00:00 2007 239 250 IEEE Computer Society cache consistency http://www.citeulike.org/user/yongchul/article/2306032 <i>(1992), pp. 419-431.</i> A Performance Study of Alternative Object Faulting and Pointer Swizzling Strategies Seth White David Dewitt (1992), pp. 419-431. 2008-01-30T06:04:48-00:00 1992 419 431 Morgan Kaufmann Publishers Inc. cache oodb performance http://www.citeulike.org/user/yijunyu/article/822228 <i>(2004)</i><br /><br />Syntax Tree, indicating that the intermediate format to represent programs also contains information encoded as polyhedra). The Omega-library [97] is used extensively to simplify Presburger formula and to convert them into sets of disjoint polytopes. The Polylib [138, 187] library is used to perform operations on polytopes, such as intersection, union, and Clauss' interpolation method for enumerating [50]. Furthermore, the analytical enumeration method described in section 4.4 has been... Software Methods to Improve Data Locality and Cache Behavior K Beyls (2004) 2006-08-30T15:48:12-00:00 2004 cache locality performance http://www.citeulike.org/user/weqa/article/1447219 <i>(2004), pp. 435-460.</i><br /><br />Modeling user activities on the Web has value both for content providers and consumers. Consumers may appreciate better responsiveness as a result of pre-calculating and of pre-loading content into a local cache in advance of their requests. A user requesting content that can be served by the cache is able to avoid the delays inherent in the Web, such as congested networks and slow servers. Additionally, consumers may find adaptive and personalized Web sites that can make... Learning web request patterns Brian Davison (2004), pp. 435-460. 2007-07-10T18:56:30-00:00 2004 435 460 Springer cache predict prefetching speculative web http://www.citeulike.org/user/visit0r/article/272200 <i>Vol. 26, No. 4. (April 1991), pp. 75-84.</i> The effect of context switches on cache performance Jeffrey Mogul Anita Borg doi:10.1145/106972.106982 Vol. 26, No. 4. (April 1991), pp. 75-84. 2005-08-03T12:34:35-00:00 1991 0362-1340 26 4 75 84 ACM Press cache context-switch context-switch-overhead http://www.citeulike.org/user/visit0r/article/2123616 <i>(1989), pp. 2-15.</i> Evaluating the performance of four snooping cache coherency protocols SJ Eggers RH Katz doi:10.1145/74925.74927 (1989), pp. 2-15. 2007-12-15T11:42:16-00:00 1989 0163-5964 2 15 ACM cache cache-coherency http://www.citeulike.org/user/tomhebbron/article/2926575 <i>(2007), pp. 16-16.</i> Pipeline spectroscopy TR Puzak A Hartstein V Srinivasan PG Emma (2007), pp. 16-16. 2008-06-25T18:15:24-00:00 2007 16 16 USENIX Association cache http://www.citeulike.org/user/thiagomanel/article/2068697 <i>SIGOPS Oper. Syst. Rev., Vol. 23, No. 5. (1989), pp. 202-210.</i> Leases: an efficient fault-tolerant mechanism for distributed file cache consistency C Gray D Cheriton doi:10.1145/74851.74870 SIGOPS Oper. Syst. Rev., Vol. 23, No. 5. (1989), pp. 202-210. 2007-12-06T19:20:04-00:00 1989 SIGOPS Oper. Syst. Rev. 23 5 202 210 ACM cache caching consistence distributed fault lease http://www.citeulike.org/user/sugaya/article/1354210 <i>IEEE Trans. Comput., Vol. 48, No. 3. (March 1999), pp. 352-360.</i> An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors Yeimkuan Chang Laxmi Bhuyan doi:10.1109/12.755001 IEEE Trans. Comput., Vol. 48, No. 3. (March 1999), pp. 352-360. 2007-06-01T06:48:15-00:00 1999 IEEE Trans. Comput. 0018-9340 48 3 352 360 IEEE Computer Society architecture cache coherence shared-memory http://www.citeulike.org/user/soumya/article/1166097 <i>High Performance Computing, 1997. Proceedings. Fourth International Conference on (1997), pp. 94-99.</i><br /><br />We look at a number of policies for managing a file system cache in a Web server. Traces from NCSA World Wide Web (WWW) server are used in this study. We study several caching policies for improving the overall performance of such a server and show that request response time can be improved by some of the replacement policies that take size of the request into account. It is shown that least frequently used (LFU) performs well when cache sizes are small (<16 MB) and SpacexAge replacement policy performs consistently better than LRU. We show that previously proposed cache sharing policies improve performance significantly in clustered Web servers Effectiveness of caching policies for a Web server Narasimha High Performance Computing, 1997. Proceedings. Fourth International Conference on (1997), pp. 94-99. 2007-03-15T21:06:35-00:00 1997 High Performance Computing, 1997. Proceedings. Fourth International Conference on 94 99 cache http://www.citeulike.org/user/sharshera/article/2091007 <i>(2002)</i><br /><br />Tiling has long been used to improve cache performance. Recursion has recently been used as a cache-oblivious method of improving cache performance. Both of these techniques are normally applied to dense linear algebra problems. We develop new implementations by means of these two techniques for the fundamental graph problem of Transitive Closure, namely the Floyd-Warshall Algorithm, and prove their optimality with respect to processor-memory traffic. Using these implementations we show up to... Optimizing Graph Algorithms for Improved Cache Performance J Park M Penner V Prasanna (2002) 2007-12-11T18:33:46-00:00 2002 cache conscious floydwarshall http://www.citeulike.org/user/quanpt/article/2842513 <i>(2007), pp. 445-454.</i> Emulating Optimal Replacement with a Shepherd Cache Kaushik Rajan Govindarajan Ramaswamy doi:10.1109/MICRO.2007.14 (2007), pp. 445-454. 2008-05-28T18:48:16-00:00 2007 445 454 IEEE Computer Society cache comparch noise predictor http://www.citeulike.org/user/quanpt/article/2766845 <i>High-Performance Computer Architecture, 2006. The Twelfth International Symposium on (2006), pp. 145-154.</i><br /><br />Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percentage of data brought into the cache that is actually used. Our experiments showed that Level 1 data cache has a utilization of only about 57%. In this paper, we show that the useless data in a cache block (cache noise) is highly predictable. This can be used to bring only the to-be-referenced data into the cache on a cache miss, reducing the energy, cache space, and bandwidth wasted on useless data. Cache noise prediction is based on the last words usage history of each cache block. Our experiments showed that a code-context predictor is the best performing predictor and has a predictability of about 95%. In a code context predictor, each cache block belongs to a code context determined by the upper order PC bits of the instructions that fetched the cache block. When applying cache noise prediction to L1 data cache, we observed about 37% improvement in cache utilization, and about 23% and 28% reduction in cache energy consumption and bandwidth requirement, respectively. Cache noise mispredictions increased the miss rate by 0.1% and had almost no impact on instructions per cycle (IPC) count. When compared to a sub-blocked cache, fetching the to-be-referenced data resulted in 97% and 44% improvement in miss rate and cache utilization, respectively. The sub-blocked cache had a bandwidth requirement about 35% of the cache noise prediction based approach. Increasing the cache efficiency by eliminating noise P Pujara A Aggarwal doi:10.1109/HPCA.2006.1598121 High-Performance Computer Architecture, 2006. The Twelfth International Symposium on (2006), pp. 145-154. 2008-05-07T15:41:59-00:00 2006 High-Performance Computer Architecture, 2006. The Twelfth International Symposium on 145 154 cache noise predictor http://www.citeulike.org/user/pedagand/article/1819160 <i>(2005), pp. 129-142.</i> Shark: scaling file servers via cooperative caching Siddhartha Annapureddy Michael Freedman David Mazières doi:10.1145/225535.225537 (2005), pp. 129-142. 2007-10-25T06:49:15-00:00 2005 129 142 USENIX Association cache dht p2p http://www.citeulike.org/user/pedagand/article/1926232 <i>SIGOPS Oper. Syst. Rev., Vol. 36, No. SI. (2002), pp. 345-360.</i> The effectiveness of request redirection on CDN robustness Limin Wang Vivek Pai Larry Peterson doi:10.1145/844128.844160 SIGOPS Oper. Syst. Rev., Vol. 36, No. SI. (2002), pp. 345-360. 2007-11-16T12:24:29-00:00 2002 SIGOPS Oper. Syst. Rev. 0163-5980 36 SI 345 360 ACM cache congestion-control ddos p2p http://www.citeulike.org/user/pedagand/article/3042086 <i>No. 92-19. (1992)</i><br /><br />. To deepen our quantitative understanding of the performance of lazy evaluation, we have studied the cache behaviour of a benchmark of functional programs. The compiler, based on the G-machine style of graph reduction, has been modified to insert monitoring code into the executable that records instruction and data references at run time. The resulting address trace is used to drive a cache simulator that computes statistics like miss rates and traffic ratios. A number of experiments with... Cache Behaviour of Lazy Functional Programs K Langendoen DJ Agterkamp No. 92-19. (1992) 2008-07-25T09:15:30-00:00 1992 92-19 cache haskell lazy-language optimization http://www.citeulike.org/user/openhacker/article/1314432 <i>IEEE Transactions on Computers, Vol. 44, No. 10. (1995), pp. 1223-1235.</i><br /><br />In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (a) developing a high level program to measure the design and performance of the cache and TLB for any machine; (b) using those measurements, along with published miss ratio data, to improve the accuracy of our run time predictions; (c) using our analysis tools... Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes Rafael Saavedra Alan Smith IEEE Transactions on Computers, Vol. 44, No. 10. (1995), pp. 1223-1235. 2007-05-21T06:11:59-00:00 1995 IEEE Transactions on Computers 44 10 1223 1235 cache http://www.citeulike.org/user/openhacker/article/1230907 <i>Soft\-waredash Prac\-tice and Experience, Vol. 30, No. 5. (2000), pp. 567-587.</i><br /><br />The performance of memory-intensive applications tends to be poor due to the high overhead added by the swapping mechanism. The same problem may be found in highly-loaded multi-programming systems where all running applications have to use the swap space in order to be able to execute at the same time. In this paper, we present a solution to these problems. The idea consists of compressing the swapped pages and keeping them in a swap cache whenever possible. The idea of a compressed swap ... Swap compression: resurrecting old ideas Toni Cortes Yolanda Becerra Raúl Cervera Soft\-waredash Prac\-tice and Experience, Vol. 30, No. 5. (2000), pp. 567-587. 2007-04-17T06:32:24-00:00 2000 Soft\-waredash Prac\-tice and Experience 30 5 567 587 cache http://www.citeulike.org/user/openhacker/article/1230905 <i>(2004)</i><br /><br />Many situations call for an estimation of the execution time of applications, e.g., during design or evaluation of computer systems. In this paper we focus on large applications where the execution times heavily depend on the performance of the memory system. Since such applications are computationally expensive, direct simulation is not an option and an analytical model is called for. Effectiveness of Simple Memory Models for Performance Prediction I Chihaia T Gross (2004) 2007-04-17T06:31:22-00:00 2004 cache http://www.citeulike.org/user/openhacker/article/1230902 <i>(2005)</i><br /><br />The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowledge of the memory hierarchy parameters of that platform. In practice, this information is poorly documented if at all. Moreover, there is growing interest in self-tuning, autonomic software systems that can optimize themselves for di#erent platforms; these systems must determine memory hierarchy parameters automatically ... Automatic measurement of memory hierarchy parameters K Yotov K Pingali P Stodghill (2005) 2007-04-17T06:27:26-00:00 2005 cache http://www.citeulike.org/user/openhacker/article/1230895 <i>No. HPL-2002-313. (November August 2002)</i><br /><br />lmbench3 extends the lmbench2 system to measure a system'sperformance under scalable load to make it possible to assess parallel and distributed computer performance with the same power and flexibility that lmbench2 brought to uni-processor performance analysis. There is a new timing harness, benchmp, designed to measure performance at specific levels of parallel (simultaneous) load, and most existing benchmarks have been converted to use the new harness. lmbench is a micro-benchmark suite... lmbench3: measuring scalability Carl Staelin No. HPL-2002-313. (November August 2002) 2007-04-17T06:20:46-00:00 2002 HPL-2002-313 cache http://www.citeulike.org/user/openhacker/article/330245 <i>(1996), pp. 279-294.</i><br /><br />lmbench is a micro-benchmark suite designed to focus attention on the basic building blocks of many common system applications, such as databases, simulations, software development, and networking. In almost all cases, the individual tests are the result of analysis and isolation of a customer's actual performance problem. These tools can be, and currently are, used to compare different system implementations from different vendors. In several cases, the benchmarks have uncovered previously... lmbench: Portable Tools for Performance Analysis Larry Mcvoy Carl Staelin (1996), pp. 279-294. 2005-09-22T19:01:47-00:00 1996 279 294 cache http://www.citeulike.org/user/openhacker/article/1230894 <i></i><br /><br />There is growing interest in self-optimizing computing systems that can optimize their own behavior on different platforms without manual intervention. Examples of successful self-optimizing systems are ATLAS, which generates Basic Linear Algebra Subroutine (BLAS) Libraries, and FFTW, which generates FFT libraries. Self-optimizing systems need values for hardware parameters such as the number of registers of various types and the capacities of caches at various levels. For example, ATLAS uses... X-Ray: A Tool for Automatic Measurement of Hardware Parameters Kamen Yotov Keshav Pingali Paul Stodghill 2007-04-17T06:19:54-00:00 cache http://www.citeulike.org/user/openhacker/article/1230893 <i>IEEE Transactions on Computers, Vol. 44, No. 10. (1995), pp. 1223-1235.</i><br /><br />In previous research, we have developed and presented a model for measuring machines and analyzing programs, and for accurately predicting the running time of any analyzed program on any measured machine. That work is extended here by: (a) developing a high level program to measure the design and performance of the cache and TLB for any machine; (b) using those measurements, along with published miss ratio data, to improve the accuracy of our run time predictions; (c) using our analysis tools... Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes Rafael Saavedra Alan Smith IEEE Transactions on Computers, Vol. 44, No. 10. (1995), pp. 1223-1235. 2007-04-17T06:19:17-00:00 1995 IEEE Transactions on Computers 44 10 1223 1235 cache http://www.citeulike.org/user/openhacker/article/1230883 <i>(July 2000), pp. 383-390.</i><br /><br />We develop an analytic model, and a set of microbenchmark programs for the measurement of the structural parameters of data cache memories and data TLBs. Running under Linux, our microbenchmarks accurately measure data cache capacity, data cache line size, data cache associativity, effective cache latency, effective data path parallelism, data TLB size, data TLB associativity, and TLB latency. We present experimental results from running our microbenchmarks on Pentium II and Pentium III... Measuring Data Cache and TLB Parameters Under Linux Clark Thomborson Yuanhua Yu (July 2000), pp. 383-390. 2007-04-17T06:05:38-00:00 2000 383 390 Society for Computer Simulation International cache http://www.citeulike.org/user/openhacker/article/1230869 <i>(October 1998), pp. 376-383.</i><br /><br />We extend prior research by Saavedra and Smith on designing microbenchmarks to measure cache performance. Unlike Saavedra and Smith, we characterise read accesses separately from write accesses; we determine whether a cache allocates on write; we can detect write-back and write-through policies; and we do not assume that the address mapping function is a bit-selection. We present experimental results for two CPU/cache structures, a 200 MHz Pentium with MMX and a 180 MHz Pentium Pro. 1.... Data Cache Parameter Measurements Li Enyou Clark Thomborson (October 1998), pp. 376-383. 2007-04-17T06:04:32-00:00 1998 376 383 cache http://www.citeulike.org/user/openhacker/article/1230862 <i>(2002)</i><br /><br />Many programs execution speed suffer from cache misses. These can be reduced on three different levels: the hardware level, the compiler level and the algorithm level. Much work has been done on the hardware level and the compiler level, however relatively little work has been done on assisting the programmer to increase the locality in his programs. In this paper, a method is proposed to visualize the locality which is not exploited by the cache hardware, based on the reuse distance metric.... Visualization enables the programmer to reduce cache misses K Beyls E D'Hollander Y Yu (2002) 2007-04-17T06:01:39-00:00 2002 cache http://www.citeulike.org/user/openhacker/article/1230857 <i>(2001)</i><br /><br />The global cache misses ratio of a program does not reveal the time distribution of the memory reference patterns in detail. On the other hand, cache visualization is hampered by the huge amount of memory references to display. Therefore, many visualizers focus on a snapshot of the cache content, instead of viewing all memory transactions. In this paper, a cache visualizer is introduced which presents the integral cache behavior of a program in several complementary views. The density view of... Visualizing the impact of cache on the program execution Y Yu K Beyls E D'Hollander (2001) 2007-04-17T05:58:17-00:00 2001 cache http://www.citeulike.org/user/openhacker/article/1320036 <i></i><br /><br />The study and understanding of memory hierarchy behavior is essential, as it is critical to current systems performance. The design of optimising environments and compilers, which allow the guidance of program transformation applications in order to improve cache performance with as little user intervention as possible, is particularly interesting. In this paper we introduce a fast analytical modelling technique that is suitable for arbitrary set-associative caches with LRU replacement policy,... A compiler tool to predict memory hierarchy performance of scientific codes B Fraguela R Doallo J No E Zapata 2007-05-22T21:06:20-00:00 cache http://www.citeulike.org/user/myui/article/1816388 <i>(2001), pp. 169-180.</i> Weaving Relations for Cache Performance Anastassia Ailamaki David Dewitt Mark Hill Marios Skounakis (2001), pp. 169-180. 2007-10-24T18:06:55-00:00 2001 169 180 Morgan Kaufmann Publishers Inc. 2001 cache column-oriented dbms dsm io pax storage vldb http://www.citeulike.org/user/myui/article/2792244 <i>(1993)</i><br /><br />False sharing occurs when processors in a shared-memory parallel system make references to different data objects within the same coherence block (cache line or page), thereby inducing "unnecessary" coherence operations. False sharing is widely believed to be a serious problem for parallel program performance, but a precise definition and quantification of the problem has proven to be elusive. We explain why. In the process, we present a variety of possible definitions for false sharing, and... False Sharing and its Effect on Shared Memory Performance William Bolosky Michael Scott (1993) 2008-05-13T02:13:40-00:00 1993 cache cache_coherence falsesharing multiproc smp http://www.citeulike.org/user/myui/article/2792231 <i>IEEE Trans. Comput., Vol. 43, No. 6. (June 1994), pp. 651-663.</i> False Sharing and Spatial Locality in Multiprocessor Caches J Torrellas HS Lam JL Hennessy IEEE Trans. Comput., Vol. 43, No. 6. (June 1994), pp. 651-663. 2008-05-13T02:06:12-00:00 1994 IEEE Trans. Comput. 0018-9340 43 6 651 663 IEEE Computer Society cache cache_coherence falsesharing multiproc http://www.citeulike.org/user/myui/article/2811914 <i>SIGPLAN Not., Vol. 32, No. 7. (July 1997), pp. 90-99.</i> Tradeoffs between false sharing and aggregation in software distributed shared memory Cristiana Amza Alan Cox Karthick Rajamani Willy Zwaenepoel doi:10.1145/263767.263778 SIGPLAN Not., Vol. 32, No. 7. (July 1997), pp. 90-99. 2008-05-19T05:23:25-00:00 1997 SIGPLAN Not. 0362-1340 32 7 90 99 ACM cache cache_coherence dsm falsesharing interesting tradeoff http://www.citeulike.org/user/myui/article/2560569 <i>(2004), pp. 191-202.</i> Buffering databse operations for enhanced instruction cache performance Jingren Zhou Kenneth Ross doi:10.1145/1007568.1007592 (2004), pp. 191-202. 2008-03-19T12:32:09-00:00 2004 191 202 ACM 2004 cache dbms modern-hardware sigmod http://www.citeulike.org/user/myui/article/1466779 <i>(2005), pp. 33-33.</i> SARC: sequential prefetching in adaptive replacement cache Binny Gill Dharmendra Modha doi:10.1109/MC.2004.1297303 (2005), pp. 33-33. 2007-07-19T08:36:03-00:00 2005 33 33 USENIX Association bufman cache ibm prefetch http://www.citeulike.org/user/myui/article/1203136 <i>(2002), pp. 76-83.</i> A fine-grained replacement strategy for XML query cache Li Chen Song Wang Elizabeth Cash Burke Ryder Ian Hobbs Elke Rundensteiner doi:10.1145/584931.584947 (2002), pp. 76-83. 2007-04-02T16:16:06-00:00 2002 76 83 ACM Press bufman cache query_cache xml http://www.citeulike.org/user/myui/article/1321642 <i>(2004), pp. 20-30.</i> Inter-reference gap distribution replacement: an improved replacement algorithm for set-associative caches Masamichi Takagi Kei Hiraki doi:10.1145/1006209.1006213 (2004), pp. 20-30. 2007-05-23T15:25:18-00:00 2004 20 30 ACM Press bufman cache irgs http://www.citeulike.org/user/myui/article/1466770 <i>(2005), pp. 157-168.</i> The performance impact of kernel prefetching on buffer cache replacement algorithms Ali Butt Chris Gniady Charlie Hu doi:10.1145/1064212.1064231 (2005), pp. 157-168. 2007-07-19T08:23:13-00:00 2005 0163-5999 157 168 ACM Press bufman cache filesystem kernel prefetch http://www.citeulike.org/user/myui/article/1468010 <i>SIGMETRICS Perform. Eval. Rev., Vol. 30, No. 1. (June 2002), pp. 31-42.</i> LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance Song Jiang Xiaodong Zhang doi:10.1145/511399.511340 SIGMETRICS Perform. Eval. Rev., Vol. 30, No. 1. (June 2002), pp. 31-42. 2007-07-19T22:53:11-00:00 2002 SIGMETRICS Perform. Eval. Rev. 30 1 31 42 ACM Press bufman cache irgs http://www.citeulike.org/user/myui/article/1466765 <i>(1995), pp. 188-197.</i> A study of integrated prefetching and caching strategies Pei Cao Edward Felten Anna Karlin Kai Li doi:10.1145/223587.223608 (1995), pp. 188-197. 2007-07-19T08:20:16-00:00 1995 188 197 ACM Press bufman cache prefetch http://www.citeulike.org/user/myui/article/1466763 <i>SIGOPS Oper. Syst. Rev., Vol. 29, No. 5. (December 1995), pp. 79-95.</i> Informed prefetching and caching RH Patterson GA Gibson E Ginting D Stodolsky J Zelenka doi:10.1145/224057.224064 SIGOPS Oper. Syst. Rev., Vol. 29, No. 5. (December 1995), pp. 79-95. 2007-07-19T08:18:48-00:00 1995 SIGOPS Oper. Syst. Rev. 29 5 79 95 ACM Press bufman cache prefetch http://www.citeulike.org/user/myui/article/1089874 <i>(April 2005), pp. 35-35.</i><br /><br />With the ever-growing performance gap between memory systems and disks, and rapidly improving CPU performance, virtual memory (VM) management becomes increasingly important for overall system performance. However, one of its critical components, the page replacement policy, is still dominated by CLOCK, a replacement policy developed almost 40 years ago. While pure LRU has an unaffordable cost in VM, CLOCK simulates the LRU replacement algorithm with a low cost acceptable in VM management. Over... CLOCK-Pro: An Effective Improvement of the CLOCK Replacement Song Jiang Feng Chen Xiaodong Zhang (April 2005), pp. 35-35. 2007-02-06T02:37:40-00:00 2005 35 35 bufman cache clock http://www.citeulike.org/user/myui/article/2366342 <i>Computer, Vol. 23, No. 6. (June 1990), pp. 12-24.</i> A Survey of Cache Coherence Schemes for Multiprocessors Per Stenström Computer, Vol. 23, No. 6. (June 1990), pp. 12-24. 2008-02-12T15:14:28-00:00 1990 Computer 0018-9162 23 6 12 24 IEEE Computer Society Press cache cache_coherence multiproc http://www.citeulike.org/user/myui/article/1041357 <i>(1981), pp. 87-95.</i> WSCLOCK - a simple and effective algorithm for virtual memory management Richard Carr John Hennessy doi:10.1145/800216.806596 (1981), pp. 87-95. 2007-01-14T20:25:32-00:00 1981 0163-5980 87 95 ACM Press bufman cache classic working-set http://www.citeulike.org/user/mwmarkland/article/1887383 <i>ACM Comput. Surv., Vol. 14, No. 3. (September 1982), pp. 473-530.</i> Cache Memories Alan Smith doi:10.1145/356887.356892 ACM Comput. Surv., Vol. 14, No. 3. (September 1982), pp. 473-530. 2007-11-09T05:28:01-00:00 1982 ACM Comput. Surv. 0360-0300 14 3 473 530 ACM cache http://www.citeulike.org/user/muli/article/1710864 <i>SIGARCH Comput. Archit. News, Vol. 35, No. 2. (May 2007), pp. 358-368.</i> Comparing memory systems for chip multiprocessors Jacob Leverich Hideho Arakida Alex Solomatnikov Amin Firoozshahian Mark Horowitz Christos Kozyrakis doi:10.1145/1273440.1250707 SIGARCH Comput. Archit. News, Vol. 35, No. 2. (May 2007), pp. 358-368. 2007-09-30T09:34:28-00:00 2007 SIGARCH Comput. Archit. News 0163-5964 35 2 358 368 ACM Press arch architecture cache isca http://www.citeulike.org/user/miteshjain/article/1476300 <i>High Performance Computer Architecture, 2004. HPCA-10. Proceedings. 10th International Symposium on (2004), pp. 288-299.</i><br /><br />Using alternative cache indexing/hashing functions is a popular technique to reduce conflict misses by achieving a more uniform cache access distribution across the sets in the cache. Although various alternative hashing functions have been demonstrated to eliminate the worst case conflict behavior, no study has really analyzed the pathological behavior of such hashing functions that often result in performance slowdown. We present an in-depth analysis of the pathological behavior of cache hashing functions. Based on the analysis, we propose two new hashing functions: prime modulo and prime displacement that are resistant to pathological behavior and yet are able to eliminate the worst case conflict behavior in the L2 cache. We show that these two schemes can be implemented in fast hardware using a set of narrow add operations, with negligible fragmentation in the L2 cache. We evaluate the schemes on 23 memory intensive applications. For applications that have nonuniform cache accesses, both prime modulo and prime displacement hashing achieve an average speedup of 1.27 compared to traditional hashing, without slowing down any of the 23 benchmarks. We also evaluate using multiple prime displacement hashing functions in conjunction with a skewed associative L2 cache. The skewed associative cache achieves a better average speedup at the cost of some pathological behavior that slows down four applications by up to 7%. Using prime numbers for cache indexing to eliminate conflict misses M Kharbutli K Irwin Y Solihin J Lee High Performance Computer Architecture, 2004. HPCA-10. Proceedings. 10th International Symposium on (2004), pp. 288-299. 2007-07-24T08:04:44-00:00 2004 High Performance Computer Architecture, 2004. HPCA-10. Proceedings. 10th International Symposium on 288 299 architecture cache computer indexing number prime http://www.citeulike.org/user/meisner/article/2638305 <i>IEEE Micro, Vol. 28, No. 1. (January 2008), pp. 60-68.</i> Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability Xiaoyao Liang Ramon Canal Gu-Yeon Wei David Brooks doi:10.1109/MM.2008.12 IEEE Micro, Vol. 28, No. 1. (January 2008), pp. 60-68. 2008-04-07T17:26:30-00:00 2008 IEEE Micro 0272-1732 28 1 60 68 IEEE Computer Society Press cache dram power sram vlsi http://www.citeulike.org/user/mamadoudiao/article/2790873 <i>IEEE Transactions on Computers, Vol. 48, No. 2. (1999), pp. 121-133.</i><br /><br />Prefetching is one approach to reducing the latency of memory operations in modern computer systems. In this paper, we describe the Markov prefetcher. This prefetcher acts as an interface between the on-chip and off-chip cache, and can be added to existing computer designs. The Markov prefetcher is distinguished by prefetching multiple reference predictions from the memory subsystem, and then prioritizing the delivery of those references to the processor. This design results in a prefetching... Prefetching Using Markov Predictors Doug Joseph Dirk Grunwald IEEE Transactions on Computers, Vol. 48, No. 2. (1999), pp. 121-133. 2008-05-12T21:28:05-00:00 1999 IEEE Transactions on Computers 48 2 121 133 cache markov-prefetching memory-access-pattern prefetching http://www.citeulike.org/user/mamadoudiao/article/2698596 <i>(1991), pp. 40-52.</i> Software prefetching David Callahan Ken Kennedy Allan Porterfield doi:10.1145/106972.106979 (1991), pp. 40-52. 2008-04-22T00:29:18-00:00 1991 40 52 ACM cache prefetching software-prefetching