CiteULike: Tag pll

Channel acquisition and tracking for DS-CDMA uplink transmissions

C Carbonelli — 2008-05-20T12:02:39-00:00

Communications, IEEE Transactions on, Vol. 53, No. 11. (2005), pp. 1930-1939.

This paper deals with channel acquisition and tracking for the uplink of direct-sequence code-division multiple-access systems. The transmission medium is characterized by multipath propagation, and the goal is to estimate the time-varying channel impulse response (CIR) for a new user entering the system. Channel acquisition is pursued through maximum-likelihood techniques. The resulting scheme may be too complex in some applications, as it requires the online inversion of a large matrix. Therefore, we also consider a simpler solution based on the least-squares (LS) criterion. Channel tracking is performed through weighted LS methods. At each signaling interval, the CIR estimate is updated using data decisions and exploiting the inverse of the interference covariance matrix to mitigate the near-far problem. Performance is assessed by simulation in a scenario inspired by the frequency-division duplexing component of the universal mobile telecommunications system. The acquisition/tracking algorithms are found to be resistant to multiuser interference and suitable for transmissions over fast-fading channels.

Channel tracking for RAKE receivers in closely spaced multipath environments

G Fock — 2008-05-20T12:01:59-00:00

Selected Areas in Communications, IEEE Journal on, Vol. 19, No. 12. (2001), pp. 2420-2431.

This paper deals with the problem of channel tracking for RAKE receivers in propagation environments characterized by closely spaced multipath components. After outlining why conventional single-path channel tracking algorithms fail in such scenarios, several new estimation algorithms are developed that are tailored to channels with closely spaced multipaths. This is achieved by removing or minimizing self-interference caused by multipath components. Other interfering users are treated as noise. Both timing tracking and phasor tracking and their interaction are covered in this paper. The derived algorithms are benchmarked against perfect channel knowledge on one hand and conventional tracking algorithms on the other hand, both in a UMTS test scenario. In moderate scenarios, the use of these new algorithms leads to performance improvements of up to 2 dB, in terms of signal-to-noise ratio (SNR) at moderate bit error rates, and even manages to track the channel in conditions where conventional tracking algorithms fail completely

Cycle Slips in Phase-Locked Loops: A Tutorial Survey

G Ascheid — 2008-05-20T11:55:05-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 30, No. 10. (1982), pp. 2228-2241.

Cycle slips in phase-locked loops are statistical, nonlinear phenomena. This makes a mathematical analysis extremely difficult. As a consequence, the results of such an analysis are not easily accessible to the practicing engineer. It is the purpose of this survey paper to present a self-contained discussion of cycle slips in phase-locked loop avoiding advanced mathematical tools. Based on the results of an extensive experimental study we explain the underlying principle of the complex interaction between nonlinearity and noise. The results are complemented by simple, approximate analysis which agrees well with the experimental findings. In addition, we present a new and complete set of diagrams on cycle slip statistics not presently available in the literature.

Dual frequency modulation with two cantilevers in series: a possible means to rapidly acquire tip–sample interaction force curves with dynamic AFM

Santiago Solares — 2008-05-06T17:36:42-00:00

Measurement Science and Technology, Vol. 19, No. 5. (2008), 055502.

One common application of atomic force microscopy (AFM) is the acquisition of tip-sample interaction force curves. However, this can be a slow process when the user is interested in studying non-uniform samples, because existing contact- and dynamic-mode methods require that the measurement be performed at one fixed surface point at a time. This paper proposes an AFM method based on dual frequency modulation using two cantilevers in series, which could be used to measure the tip-sample interaction force curves and topography of the entire sample with a single surface scan, in a time that is comparable to the time needed to collect a topographic image with current AFM imaging modes. Numerical simulation results are provided along with recommended parameters to characterize tip-sample interactions resembling those of conventional silicon tips and carbon nanotube tips tapping on silicon surfaces.

Injection- and phase-locking techniques for beam control [antenna arrays]

RA York — 2008-05-09T06:40:42-00:00

Microwave Theory and Techniques, IEEE Transactions on, Vol. 46, No. 11. (1998), pp. 1920-1929.

Applications of millimeter-wave radar, imaging, and communication technology requires cost-effective implementation of intelligent scanning antenna systems. Injection-locking and phase-locked-loop (PLL) techniques can be used to achieve synchronous operation of a number of antenna array elements, and allow for the manipulation of the phase distribution without additional phase-shifting circuitry, suggesting a potential for low-cost beam-scanning systems. This paper describes a number of techniques, with an assessment of some remaining technical challenges for practical implementation

Phase locked loop using delay compensation techniques

F Spagna — 2008-05-22T09:06:28-00:00

Computers and Communications, 2000. Proceedings. ISCC 2000. Fifth IEEE Symposium on (2000), pp. 417-423.

This paper illustrates a modification to a basic phase locked loop (PLL) topology aimed at compensating the effects of loop latency. The technique, developed to address the performance degradation observed in high latency PLL topologies as is the case of Viterbi based decision directed read channel timing recovery, is readily applicable to digital baseband communication receivers

Phase-locked-loop control of active microstrip patch antennas

JW Andrews — 2008-05-09T06:40:39-00:00

Microwave Theory and Techniques, IEEE Transactions on, Vol. 50, No. 1. (2002), pp. 201-206.

Active patch antennas are simple to fabricate, compact, and low cost, but have inherently poor phase noise and stability. In this paper, a phase-locked loop (PLL) integrated with a 4-GHz active patch antenna was investigated in order to reduce the phase noise and stabilize the frequency of the oscillator. Both these aims were realized by careful integration and optimization of the PLL parameters. Experimental results showed that a phase noise reduction in excess of 55 dB was achieved using this technique. A standalone voltage-controlled oscillator and passive patch technique can provide lower phase noise, but the active patch lends itself to effective integration. Measurement techniques were demonstrated to measure the phase noise and stability of the patch oscillator

Noise analysis of phase-locked loops

A Mehrotra — 2008-06-03T18:59:27-00:00

Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on (2000), pp. 277-282.

This work addresses the problem of noise analysis of phase locked loops (PLLs). The problem is formulated as a stochastic differential equation and is solved in presence of circuit white noise sources yielding the spectrum of the PLL output. Specifically, the effect of loop filter characteristics, phase-frequency detector and phase noise of the open loop voltage controlled oscillator (VCO) on the PLL output spectrum is quantified. These results are derived using a full nonlinear analysis of the VCO in the feedback loop and cannot be predicted using traditional linear analyses or the phase noise analysis of open loop oscillators. The computed spectrum matches well with measured results, specifically, the shape of the output spectrum matches very well with measured PLL output spectra reported in the literature for different kinds of loop filters and phase detectors. The PLL output spectrum computation only requires the phase noise of the VCO, loop filter and phase detector noise, phase detector gain and loop filter transfer function and does not require the transient simulation of the entire PLL which can be very expensive. The noise analysis technique is illustrated with some examples

PLL/DLL system noise analysis for low jitter clock synthesizer design

Beomsup Kim — 2008-05-22T09:05:58-00:00

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, Vol. 4 (1994), pp. 31-34 vol.4.

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement

Methodology for on-chip adaptive jitter minimization in phase-locked loops

M Mansuri — 2008-05-09T23:43:06-00:00

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878.

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

Phase-locked loop techniques. A survey

Guan-Chyun Hsieh — 2008-06-09T19:33:05-00:00

Industrial Electronics, IEEE Transactions on, Vol. 43, No. 6. (1996), pp. 609-615.

Phase-locked loop (PLL) is a technique which has contributed significantly toward the technology advancement in communication and motor servo control systems in the past 30 years. Inventions in PLL schemes combined with novel integrated circuit (IC) technology have made PLL devices important system components. The development of better modular PLL ICs is continuing. As a result, it is expected that they will contribute to the improvement in performance and reliability of future communication systems. They will also contribute to the development of higher accuracy and higher reliability servo control systems, such as those involved in machine tools. This paper provides a concise review of the basic PLL principles applicable to communication and servo control systems, gives the configurations of PLL applications and reports a number of popular PLL chips

Extended tracking range delay-locked loop

A Wilde — 2008-06-02T07:14:33-00:00

Communications, 1995. ICC '95 Seattle, 'Gateway to Globalization', 1995 IEEE International Conference on, Vol. 2 (1995), pp. 1051-1054 vol.2.

In spread spectrum systems PN-code tracking is a crucial performance aspect. The delay-locked loop (DLL) is an appropriate device to guarantee fine synchronization. In this paper, a modified extended tracking range DLL is proposed. In the design of a DLL there is a tradeoff between tracking jitter and tracking range. The loop noise in an extended tracking range DLL is normally increased since more correlators are used. The jitter performance is improved by selecting the two strongest extended DLL branches. This modifies the extended DLL detector S-curve only slightly while reducing the noise power in the loop considerably

A low-noise phase-locked loop design by loop bandwidth optimization

Kyoohyun Lim — 2008-05-10T14:39:00-00:00

Solid-State Circuits, IEEE Journal of, Vol. 35, No. 6. (2000), pp. 807-815.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively

The performance of the all-digital data transition tracking loop using nonlinear analysis

A Mileant — 2008-05-22T08:58:49-00:00

Communications, IEEE Transactions on, Vol. 43, No. 234. (1995), pp. 1202-1215.

This paper describes the performance of the all digital data transition tracking loop (DTTL) with coherent and noncoherent sampling using nonlinear theory. The effects of few samples per symbol and of non-commensurate sampling and symbol rates are addressed and analyzed for perfectly square pulses as well as filtered pulses. Their impact on the probability density and variance of the phase error are quantified through computer simulations. It is shown that the performance of the all-digital DTTL approaches its analog counterpart when the sampling and symbol rates are noncommensurate (i.e., the number of samples per symbol is irrational). The phase error variance for an even number of samples per symbol is also shown to degrade compared to an odd number of samples per symbol

On phase-locked loops and Kalman filters

A Patapoutian — 2008-05-22T08:58:52-00:00

Communications, IEEE Transactions on, Vol. 47, No. 5. (1999), pp. 670-672.

Driessen (1994) and Christiansen (1994) independently showed that for a specific dynamic model, the proportional-integral phase-locked loop (PLL) has the same structure as the Kalman filter. In this paper, closed-form expressions of the corresponding Kalman gain values are derived both in acquisition and tracking modes of the PLL

A Second-Order Frequency-Aided Digital Phase-Locked Loop for Doppler Rate Tracking

C Chie — 2008-05-22T09:26:06-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 28, No. 8. (1980), pp. 1431-1436.

A second-order digital phase-locked loop (DPLL) has a finite lock range which is a function of the frequency of the incoming signal to be tracked. For this reason, it is not capable of tracking an input with Doppler rate for an indefinite period of time. In this correspondence, an analytical expression for the hold-in time is derived. In addition, an all-digital scheme to alleviate this problem is proposed based on the information obtained from estimating the input signal frequency.

Near-optimal PLL design for decision-feedback carrier and timing recovery

O Yaniv — 2008-05-09T23:56:08-00:00

Communications, IEEE Transactions on, Vol. 49, No. 9. (2001), pp. 1669-1678.

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing, or other synchronization loops given the phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exist in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser linewidth. We provide an easy-to-use complete design procedure for second-order loops. We also introduce a design procedure for higher order loops for near-optimal performance. We show that using the traditional second-order loop is suboptimal when there is a delay in the loop, and also shows large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay

Near optimal PLL design for decision feedback carrier and timing recovery

D Raphaeli — 2008-05-09T23:56:05-00:00

Communications, 1999. ICC '99. 1999 IEEE International Conference on, Vol. 3 (1999), pp. 1515-1520 vol.3.

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing or other synchronization loops given phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exists in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser line width. We provide an easy to use complete design procedure for second order loops. We also introduce a design procedure for higher order loops for near optimal performance. We show that using the traditional second order loop is suboptimal when there is a delay in the loop, and also show large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay

Frequency offset tracking in OFDM based on multicarrier PLL

MR Dacca — 2008-05-13T10:45:38-00:00

MILCOM 2000. 21st Century Military Communications Conference Proceedings, Vol. 2 (2000), pp. 912-916 vol.2.

A novel algorithm for frequency offset tracking in orthogonal frequency-division multiplexing (OFDM) is proposed. The algorithm is based on decision-feedback and assumes differential reception. It makes it possible to track the frequency shift of an OFDM signal transmitted over a frequency dispersive channel. The channel is assumed to be time invariant for each OFDM sub-carrier. The processing is performed in the base band part and does not require any processing in the RF stage. A novel multicarrier phase locked loop (MPLL) for frequency shift tracking is described. The MPLL explores some unique features of the OFDM. A low-complexity real-time algorithm is obtained. It is shown that a receiver based on the suggested algorithm works well even for a relatively low signal to noise ratio (SNR) and its performance closely approaches that of differential detection without a frequency offset. We show that the proposed frequency offset compensation may be used in a tracking mode in OFDM receivers and may be implemented for high frequency (HF) communication, digital audio broadcasting, underwater acoustic communications or digital subscriber lines

Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise Conditions

U Yehuday — 2008-05-09T23:56:03-00:00

Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.

The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector

Shanfeng Cheng — 2008-06-03T19:01:26-00:00

Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on], Vol. 54, No. 6. (2007), pp. 474-478.

Phase-locked loops (PLLs) using binary phase detectors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second- order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed.

Hangup in Phase-Lock Loops

F Gardner — 2008-05-09T15:16:18-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 25, No. 10. (1977), pp. 1210-1214.

A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null. Restoring force is small in the vicinity of the reverse null, and noise causes the loop to equivocate about the null. Hangup is very troublesome when fast acquistion is needed with high reliability. One example is synchronization of digital communications. Hangups can be avoided if a large restoring force is applied for large phase errors and if equivocation is prevented. An implementation of an antihangup circuit is proposed.

A survey of digital phase-locked loops

WC Lindsey — 2008-06-03T18:59:32-00:00

Proceedings of the IEEE, Vol. 69, No. 4. (1981), pp. 410-431.

The purpose of this paper is to present a systematic survey of the theoretical/experimental work accomplished in the area of digital phase-locked loops (DPLL's) during the period of 1960 to 1980. The DPLL represents the heart of the Building blocks required in the implementation of coherent (all digital) communications and tracking receivers. This survey is particularly motivated by the fact that microprocessor technology is advancing rapidly to the extent that sophisticated and flexible signal processing algorithms for communications and control can be realized in the digital domain. In fact, it is anticipated that the use of this signal processing technology will continue to expand rapidly in the development of advanced communications and tracking receivers, e.g., all digital modems. Consequently, one major purpose of this paper is to provide the reader with a survey and an overview of the theoretical and experimental work accomplished to date, thereby offering speedy access to the techniques and hardware developments which have been presented in a scattered literature. In addition, the authors feel that a tutorial article revealing the various theories, their relationships to one another, their shortcomings, their advantages and the assumptions on which each is based, would be of tremendous value to the engineer trying to decide what particular analysis procedure is applicable to his peculiar problem. Consequently, a byproduct of this presentation will be to point out unsolved problems of practical interest. A broad class of digital modulation techniques, viz. I-Q modulations and demodulation, are studied in a rather general way.

All digital phase-locked loop: concepts, design and applications

YR Shayan — 2008-06-03T18:59:31-00:00

Radar and Signal Processing, IEE Proceedings F, Vol. 136, No. 1. (1989), pp. 53-56.

The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage-controlled oscillator, are explained. A second order DPLL is considered and analysed using the Z-transform technique. Implementation of the DPLL, based on the CMOS digital signal processor TMS 320C25, and the experimental results, are presented. Potential applications are also discussed.<<ETX>>