Sat, 26 Jul 2008 06:03:01 BST CiteULike: dcastro's library [2022 articles] http://www.citeulike.org/user/dcastro/article/2782005 CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/dcastro/article/2782005 <i>Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878.</i><br /><br />This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter. Methodology for on-chip adaptive jitter minimization in phase-locked loops M Mansuri A Hadiashar Chih-Kong Yang doi:10.1109/TCSII.2003.819124 Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878. 2008-05-09T23:43:06-00:00 2003 Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] 50 11 870 878 jitter pll time