Sat, 05 Jul 2008 05:29:32 BST CiteULike: dcastro's library [1879 articles] http://www.citeulike.org/user/dcastro/article/2782972 CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/dcastro/article/2782972 <i>Solid-State Circuits, IEEE Journal of, Vol. 35, No. 6. (2000), pp. 807-815.</i><br /><br />This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively A low-noise phase-locked loop design by loop bandwidth optimization Kyoohyun Lim Chan-Hong Park Dal-Soo Kim Beomsup Kim doi:10.1109/4.845184 Solid-State Circuits, IEEE Journal of, Vol. 35, No. 6. (2000), pp. 807-815. 2008-05-10T14:39:00-00:00 2000 Solid-State Circuits, IEEE Journal of 35 6 807 815 bandwidth design low noise pll