CiteULike: dcastro's jitter

The effect of timing jitter on the performance of a discrete multitone system

TN Zogakis — 2008-06-03T14:47:56-00:00

Communications, IEEE Transactions on, Vol. 44, No. 7. (1996), pp. 799-808.

The transmission of high-speed data over severely band-limited channels may be accomplished through the use of discrete multitone (DMT) modulation, a modulation technique that has been proposed for a number of new applications. While the performance of a DMT system has been analyzed by a number of authors, these analyses ignore the effect of timing jitter on system performance. Timing jitter becomes an increasingly important concern as higher data rates are supported and larger constellations are allowed on the DMT subchannels. Hence, in this paper, we assume that synchronization is maintained by using a digital phase-locked loop to track a pilot carrier, Given this model, we derive error rate expressions for an uncoded DMT system operating in the presence of timing jitter, and we derive an expression for the interchannel distortion that results from a varying timing offset across the DMT symbol. In addition, we investigate the performance of trellis-coded DMT modulation in the presence of timing jitter. Practical examples from the asymmetric digital subscriber line (ADSL) service are used to illustrate various results

PLL/DLL system noise analysis for low jitter clock synthesizer design

Beomsup Kim — 2008-05-22T09:05:58-00:00

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, Vol. 4 (1994), pp. 31-34 vol.4.

This paper presents an analytical model for timing jitter accumulation in ring-oscillator based phase-locked-loops (PLL). The timing jitter of the system is shown to depend on the jitter in the ring-oscillator and an accumulation factor which is inversely proportional to the bandwidth of the phase-locked-loop. Further analysis shows that for delay-locked-loops (DLL), which use an inverter delay chain that is not configured as a ring-oscillator, there is no noise enhancement since noise jitter events do not contribute to the starting point of the next clock cycle. Finally, theoretical predictions for overall jitter are compared to behavioral simulations with good agreement

Methodology for on-chip adaptive jitter minimization in phase-locked loops

M Mansuri — 2008-05-09T23:43:06-00:00

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878.

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.