CiteULike: dcastro's pll

Frequency offset tracking in OFDM based on multicarrier PLL

MR Dacca — 2008-05-13T10:45:38-00:00

MILCOM 2000. 21st Century Military Communications Conference Proceedings, Vol. 2 (2000), pp. 912-916 vol.2.

A novel algorithm for frequency offset tracking in orthogonal frequency-division multiplexing (OFDM) is proposed. The algorithm is based on decision-feedback and assumes differential reception. It makes it possible to track the frequency shift of an OFDM signal transmitted over a frequency dispersive channel. The channel is assumed to be time invariant for each OFDM sub-carrier. The processing is performed in the base band part and does not require any processing in the RF stage. A novel multicarrier phase locked loop (MPLL) for frequency shift tracking is described. The MPLL explores some unique features of the OFDM. A low-complexity real-time algorithm is obtained. It is shown that a receiver based on the suggested algorithm works well even for a relatively low signal to noise ratio (SNR) and its performance closely approaches that of differential detection without a frequency offset. We show that the proposed frequency offset compensation may be used in a tracking mode in OFDM receivers and may be implemented for high frequency (HF) communication, digital audio broadcasting, underwater acoustic communications or digital subscriber lines

A low-noise phase-locked loop design by loop bandwidth optimization

Kyoohyun Lim — 2008-05-10T14:39:00-00:00

Solid-State Circuits, IEEE Journal of, Vol. 35, No. 6. (2000), pp. 807-815.

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-μm CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively

Near-optimal PLL design for decision-feedback carrier and timing recovery

O Yaniv — 2008-05-09T23:56:08-00:00

Communications, IEEE Transactions on, Vol. 49, No. 9. (2001), pp. 1669-1678.

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing, or other synchronization loops given the phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exist in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser linewidth. We provide an easy-to-use complete design procedure for second-order loops. We also introduce a design procedure for higher order loops for near-optimal performance. We show that using the traditional second-order loop is suboptimal when there is a delay in the loop, and also shows large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay

Near optimal PLL design for decision feedback carrier and timing recovery

D Raphaeli — 2008-05-09T23:56:05-00:00

Communications, 1999. ICC '99. 1999 IEEE International Conference on, Vol. 3 (1999), pp. 1515-1520 vol.3.

A new design method is presented for the design of PLL loop filters for carrier recovery, bit timing or other synchronization loops given phase noise spectrum and noise level. Unlike the conventional designs, our design incorporates a possible large decision delay and S-curve slope uncertainty. Large decision delays frequently exists in modern receivers due to, for example, a convolutional decoder or an equalizer. The new design also applies to coherent optical communications where delay in the loop limits the laser line width. We provide an easy to use complete design procedure for second order loops. We also introduce a design procedure for higher order loops for near optimal performance. We show that using the traditional second order loop is suboptimal when there is a delay in the loop, and also show large improvements, either in the amount of allowed delay, or the phase error variance in the presence of delay

Mean Time to Lose Lock for a PLL with Loop Delay under Thermal and Phase Noise Conditions

U Yehuday — 2008-05-09T23:56:03-00:00

Communications, 2007. ICC '07. IEEE International Conference on (2007), pp. 2888-2893.

The growing demand for reliable communications leads to the need for very large mean time to lose lock (MTLL) of PLL based synchronization subsystems. These large MTLLs, of the order of months, cannot be simulated or tested in a lab. In this work a systematic approach is given to computing the MTLL of a second order PLL with parasitic delay at low SNR and high phase noise. Computed and simulated results are shown to be in good agreement for values that can be simulated.

Methodology for on-chip adaptive jitter minimization in phase-locked loops

M Mansuri — 2008-05-09T23:43:06-00:00

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Vol. 50, No. 11. (2003), pp. 870-878.

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 /spl mu/m CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

Hangup in Phase-Lock Loops

F Gardner — 2008-05-09T15:16:18-00:00

Communications, IEEE Transactions on [legacy, pre - 1988], Vol. 25, No. 10. (1977), pp. 1210-1214.

A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null. Restoring force is small in the vicinity of the reverse null, and noise causes the loop to equivocate about the null. Hangup is very troublesome when fast acquistion is needed with high reliability. One example is synchronization of digital communications. Hangups can be avoided if a large restoring force is applied for large phase errors and if equivocation is prevented. An implementation of an antihangup circuit is proposed.

Injection- and phase-locking techniques for beam control [antenna arrays]

RA York — 2008-05-09T06:40:42-00:00

Microwave Theory and Techniques, IEEE Transactions on, Vol. 46, No. 11. (1998), pp. 1920-1929.

Applications of millimeter-wave radar, imaging, and communication technology requires cost-effective implementation of intelligent scanning antenna systems. Injection-locking and phase-locked-loop (PLL) techniques can be used to achieve synchronous operation of a number of antenna array elements, and allow for the manipulation of the phase distribution without additional phase-shifting circuitry, suggesting a potential for low-cost beam-scanning systems. This paper describes a number of techniques, with an assessment of some remaining technical challenges for practical implementation

Phase-locked-loop control of active microstrip patch antennas

JW Andrews — 2008-05-09T06:40:39-00:00

Microwave Theory and Techniques, IEEE Transactions on, Vol. 50, No. 1. (2002), pp. 201-206.

Active patch antennas are simple to fabricate, compact, and low cost, but have inherently poor phase noise and stability. In this paper, a phase-locked loop (PLL) integrated with a 4-GHz active patch antenna was investigated in order to reduce the phase noise and stabilize the frequency of the oscillator. Both these aims were realized by careful integration and optimization of the PLL parameters. Experimental results showed that a phase noise reduction in excess of 55 dB was achieved using this technique. A standalone voltage-controlled oscillator and passive patch technique can provide lower phase noise, but the active patch lends itself to effective integration. Measurement techniques were demonstrated to measure the phase noise and stability of the patch oscillator