CiteULike: gantlord's fpga-design

Hardware-assisted simulated annealing with application for fast FPGA placement

Michael Wrighton — 2006-05-26T15:10:23-00:00

(2003), pp. 33-42.

Stochastic, spatial routing for hypergraphs, trees, and meshes

Randy Huang — 2006-05-26T14:27:24-00:00

(2003), pp. 78-87.

FPGA Based Processor for Hubble Space Telescope Autonomous Docking – A Case Study

Jonathan Feifarek — 2006-01-16T11:10:27-00:00

(September 2005)

Designing electronic hardware for flight projects requires balancing conflicting constraints: a short design cycle, tolerance of radiation induced effects, limited power, and flexibility to accommodate changing requirements and fixes. Our design space, consisting of three autonomous rendezvous and docking algorithms mission critical to the Hubble Space Telescope Robotic Vehicle project, presented our team with these constraints. In addition, analyses showed the processing throughputs of each algorithm exceeded the capacity of existing radiation hardened computers by two orders of magnitude. An FPGA based solution with dual redundancy approach at the FPGA level was selected. This paper discusses the challenges encountered in designing an algorithmic intensive FPGA based processor for flight and presents a case study to show how these difficulties were mitigated for the Hubble Robotic Vehicle.

Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization)

Andre Dehon — 2006-01-06T10:24:59-00:00

(1999), pp. 69-78.

FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficient silicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficient designs by allowing some LUTs to go...

FPGA-based computing in computer vision

NK Ratha — 2005-09-16T11:11:07-00:00

Computer Architecture for Machine Perception, 1997. CAMP '97. Proceedings Fourth IEEE International Workshop on (1997), pp. 128-137.

Algorithms in computer vision are characterized by (i) complex and repetitive operations; (ii) large amount of data and (iii) a variety of data interaction (e.g., point operations, neighborhood operations, global operations). Based on the computation and communication complexity, vision algorithms have been characterized into three categories: (i) low-level, (ii) intermediate-level and (iii) high-level. In this paper, we describe the usage of custom computing approach to meet the computation and communication needs of computer vision algorithms. By customizing hardware architecture for every application at the instruction level, the optimal grain size needed for the problem at hand and the instruction granularity can be matched. Field Programmable Gate Array (FPGA) based processing elements (PEs) are being used to provide this facility. Using programmable communication resources, the diverse communication requirements can be met. A vision system needs to integrate hardware for the three levels. A custom computing approach alleviates the problem of achieving optimal granularity for different stages as the same hardware gets reconfigured at a software level for different levels of the application. We demonstrate the advantages of our approach using Splash 2-a Xilinx 4010-based custom computer

A high-performance and energy-efficient architecture for floating-point based LU decomposition on FPGAs

G Govindu — 2005-09-14T09:26:41-00:00

Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International (2004), 149.

Summary form only given. We first develop a novel architecture for fixed-point LU decomposition of streaming input matrices, on FPGAs. Our architecture, based on a circular linear array, achieves the minimal latency and is resource-efficient. We then extend it, by using a stacked matrices approach, to a floating-point based architecture, which achieves the minimal effective latency. Our design objective was to develop high-throughput and energy-efficient architectures for applications, which require computing LU decomposition. We analyze (1) the impact of high-throughput, pipelined floating-point units (with different depths of pipelining and different performance) on the architecture's performance, and (2) the impact of algorithm level design on the system-wide energy dissipation. We analyze the energy dissipation by capturing algorithm and architectural details of the target FPGA device. We analyze and compare our architecture with a state-of-art architecture implemented on FPGAs with respect to latency, area and energy. Our designs achieve a 10%-60% reduction in energy over that of the state-of-art architecture.

System level integration, intellectual property, and the education of a new generation of system designers

P Lysaght — 2005-08-31T17:47:45-00:00

Systems on a Chip (Ref. No. 1998/439), IEE Colloquium on (1998), pp. 2/1-2/5.

Much of the future success of system level integration (SLI) is predicated on the emergence of a market for intellectual property cores (or virtual cores, as they are also known). Several factors contribute to the pressing need for a thriving market in intellectual property. While silicon capacity continues to increase exponentially, the productivity of designers, even when equipped with the most sophisticated computer aided design tools, falls dramatically short of what would be required to fully exploit the opportunities of SLI. The situation is exacerbated by a global shortage of experienced designers, and several other factors including the enormous cost of state-of-the-art fabrication facilities, the consumerisation of electronics, and the continuous pressure to reduce design cycle time. Design re-use, via a global market in intellectual property, is the perceived technical solution to these problems. This paper addresses some of the issues in educating and training undergraduates and postgraduate students to help fill the manpower shortfall

System-level design for FPGAs

P Lysaght — 2005-08-31T17:46:04-00:00

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on (2003), 4.

Summary form only given. The complexity of FPGAs has progressed to the point where they are likely to become the dominant platform for the majority of system on chip (SoC) design starts within the foreseeable future. Many of the system-level challenges that we first encountered with ASIC SoCs are fast becoming relevant for high end FPGAs. Functional verification and debug in particular are emerging as two of the biggest concerns. In this talk, we review the traditional and emerging approaches to system-level design used with ASIC designs and evaluate their appropriateness in the context of FPGAs. We proceed to explore how FPGA technology might present new opportunities to offset the system-level design challenges. Finally, we look at some novel approaches to the problem that exploit the unique features of FPGAs.

Future design tools for platform FPGAs

P Lysaght — 2005-08-31T17:45:31-00:00

Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on (2003), pp. 275-280.

According to current projections, programmable platforms will dominate ASIC design starts as the semiconductor industry moves to 90 nm process technology and beyond. In this paper, we assess the implications of this trend and explore the impact it will have on system-level design methodologies for FPGAs. We review current research and practice in system-level design and attempt to assess how much of the ASIC experience will be relevant to future FPGA designers.

Guest Editors' Introduction: Advances in Configurable Computing

P Lysaght — 2005-08-31T17:44:10-00:00

Design & Test of Computers, IEEE, Vol. 22, No. 2. (2005), pp. 85-89.

At times, it appears that the many definitions of configurable computing are every bit as configurable as the technology itself. For example, Wikipedia-the free, online, user-editable encyclopedia-defines configurable computing (or, synonymously, reconfigurable computing) as ".... computer processing with highly flexible computing fabrics. The principal difference when compared to using ordinary microprocessors is the ability to make substantial changes to the data path itself in addition to the control flow' (http://en.wikipedia.org/wiki/Configurable_computing).

The flexibility of configurable computing

J Villasenor — 2005-04-26T10:47:02-00:00

Signal Processing Magazine, IEEE, Vol. 15, No. 5. (1998), pp. 67-84.

There has been growing recent interest in configurable computing, which can be viewed as a hybrid between ASICs and programmable processors. Configurable computing machines are implemented with programmable logic: flexible hardware that can be structured to fit the natural organization and data flow of a computation. The enabling device for configurable computing is the field-programmable array (FPGA). For applications characterized by deeply pipelined, highly parallel, and integer arithmetic processing, configurable computing machines can outperform alternative solutions by up to an order of magnitude. The combination in a single device of dedicated hardware and rapid, submillisecond-scale reprogrammability constitutes an exciting and promising development whose implications are only just beginning to be exploited. We begin with a brief tutorial on FPGAs that describes the most common FPGA architectures and how these architectures are used to support computation, memory access, and data flow. We then present FPGAs as computing machines and focus on devices that are reconfigured during run time. Ongoing research involving FPGAs and future directions are also discussed