Sat, 05 Jul 2008 23:00:25 BST CiteULike: mmuecke's library [373 articles] http://www.citeulike.org/user/mmuecke CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/mmuecke/article/2963806 <i>Design Automation Conference, 2003. Proceedings (2003), pp. 496-501.</i><br /><br />We introduce a static error analysis technique, based on smart interval methods from affine arithmetic, to help designers translate DSP codes from full-precision floating-point to smaller finite-precision formats. The technique gives results for numerical error estimation comparable to detailed simulation, but achieves speedups of three orders of magnitude by avoiding actual bit-level simulation. We show results for experiments mapping common DSP transform algorithms to implementations using small custom floating point formats. Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling Fang RA Rutenbar M Puschel Tsuhan Chen Design Automation Conference, 2003. Proceedings (2003), pp. 496-501. 2008-07-04T12:35:19-00:00 2003 Design Automation Conference, 2003. Proceedings 496 501 error_analysis floating_point http://www.citeulike.org/user/mmuecke/article/2963801 <i>Computer Aided Design, 2003. ICCAD-2003. International Conference on (2003), pp. 275-282.</i><br /><br />Translating digital signal processing (DSP) software into its finite-precision hardware implementation is often a time-consuming task. We describe a new static analysis technique that can accurately analyze finite-precision effects arising from fixed-point implementations of DSP algorithms. The technique is based on recent interval representation methods from affine arithmetic, and the use of new probabilistic bounds. The resulting numerical error estimates are comparable to detailed statistical simulation, but achieve speedups of four to five orders of magnitude by avoiding actual bit-true simulation. We show error analysis results on both feed forward and feedback DSP kernels. Fast, accurate static analysis for fixed-point finite-precision effects in DSP designs CF Fang RA Rutenbar Tsuhan Chen doi:10.1109/ICCAD.2003.1257675 Computer Aided Design, 2003. ICCAD-2003. International Conference on (2003), pp. 275-282. 2008-07-04T12:33:21-00:00 2003 Computer Aided Design, 2003. ICCAD-2003. International Conference on 275 282 error_analysis fixedpoint http://www.citeulike.org/user/mmuecke/article/2952250 <i>ACM Trans. Math. Softw., Vol. 34, No. 3. (May 2008), pp. 1-25.</i> Anatomy of high-performance matrix multiplication Kazushige Goto Robert van de Geijn doi:10.1145/1356052.1356053 ACM Trans. Math. Softw., Vol. 34, No. 3. (May 2008), pp. 1-25. 2008-07-02T13:49:21-00:00 2008 ACM Trans. Math. Softw. 0098-3500 34 3 1 25 ACM high-performance_computing sparse_matrix http://www.citeulike.org/user/mmuecke/article/2952170 <i>Computing in Science & Engineering, Vol. 10, No. 4. (2008), pp. 41-49.</i><br /><br />The program tool Thermath now lets researchers automatically generate complete, ready-to-use Matlab functions. The examples here deal with critical-point calculations and the development of equipment models for separations in the chemical industry, but the ability to automatically generate Matlab functions is useful in many areas of science and engineering. Automatic Generation of Matlab Functions Using Mathematica and Thermath Raquel Macedo Marcelo Alfradique Marcelo Castier doi:10.1109/MCSE.2008.90 Computing in Science & Engineering, Vol. 10, No. 4. (2008), pp. 41-49. 2008-07-02T13:15:19-00:00 2008 Computing in Science & Engineering 10 4 41 49 generative_programming http://www.citeulike.org/user/mmuecke/article/2923926 <i>Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 35-39.</i> Interview<br />The 'art' of being Donald Knuth doi:10.1145/1364782.1364794 Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 35-39. 2008-06-24T15:49:45-00:00 2008 Commun. ACM 0001-0782 51 7 35 39 ACM people http://www.citeulike.org/user/mmuecke/article/2947829 <i>Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 91-97.</i> Anton, a special-purpose machine for molecular dynamics simulation David Shaw Martin Deneroff Ron Dror Jeffrey Kuskin Richard Larson John Salmon Cliff Young Brannon Batson Kevin Bowers Jack Chao Michael Eastwood Joseph Gagliardo JP Grossman Richard Ho Douglas Lerardi István Kolossváry John Klepeis Timothy Layman Christine Mcleavey Mark Moraes Rolf Mueller Edward Priest Yibing Shan Jochen Spengler Michael Theobald Brian Towles Stanley Wang doi:10.1145/1364782.1364802 Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 91-97. 2008-07-01T12:30:10-00:00 2008 Commun. ACM 0001-0782 51 7 91 97 ACM molecular_dynamics reconfigurable_platforms vlsi_design http://www.citeulike.org/user/mmuecke/article/2947326 <i>(2007), pp. 69-76.</i> A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design Libo Huang Li Shen Kui Dai Zhiying Wang doi:10.1109/ARITH.2007.5 (2007), pp. 69-76. 2008-07-01T09:57:22-00:00 2007 69 76 IEEE Computer Society floating_point vlsi_design http://www.citeulike.org/user/mmuecke/article/2947308 <i>(2000), pp. 71-77.</i><br /><br />An efficient algorithm is presented that returns the exactly rounded sum of two multiprecision floating point numbers. Depending on the input signs and exponents the algorithm distinguishes five cases. In each case, the method minimizes the number of computer words that are subject to de-normalization, addition or subtraction, and normalization. The method achieves further efficiency by trying to combine these three steps into one single pass over the mantissas. To do this, the method guesses the shift amount of the normalizing shift before the sum is known. Multiprecision floating point addition George Collins Werner Krandick doi:10.1145/345542.345585 (2000), pp. 71-77. 2008-07-01T09:52:44-00:00 2000 71 77 ACM floating_point http://www.citeulike.org/user/mmuecke/article/1851392 <i>TENCON 2005 2005 IEEE Region 10 (2005), pp. 1-6.</i><br /><br />Molecular biocomputation workflows traditionally involve days of compute time to align DNA/ protein sequences. Custom computing machines (CCMs) provide a means to dramatically reduce alignment time, and FPGAs provide a practical means to implement such CCMs. Software implementation of some sequence alignment algorithms suffer quadratic time performance, however CCM implementations may be highly parallelized and consequently provide linear time performance. Similarly, CCMs may be used to accelerate workflows or operations in a wide range of domains, often dramatically outperforming large scale clusters. Programming and integration problems limit CCM usage, though progress has been made to overcome these problems. With continued development of tools, devices, and integration solutions, CCMs on FPGAs coupled to conventional systems present an effective architecture for high performance computing. A Survey of FPGAs for Acceleration of High Performance Computing and their Application to Computational Molecular Biology T Ramdas G Egan TENCON 2005 2005 IEEE Region 10 (2005), pp. 1-6. 2007-11-01T14:47:12-00:00 2005 TENCON 2005 2005 IEEE Region 10 1 6 bioinformatics fpgasupercomputing genomesequencing molecular_docking molecular_dynamics reconfigurable_computing survey trends http://www.citeulike.org/user/mmuecke/article/2598926 <i>(2007), pp. 922-930.</i> On-board analysis of uncalibrated data for a spacecraft at mars Rebecca Castano Kiri Wagstaff Steve Chien Timothy Stough Benyang Tang doi:10.1145/1281192.1281291 (2007), pp. 922-930. 2008-03-26T15:18:27-00:00 2007 922 930 ACM svm http://www.citeulike.org/user/mmuecke/article/2926148 <i>Neural Networks, 2007. IJCNN 2007. International Joint Conference on (2007), pp. 1360-1364.</i><br /><br />We present here a hardware-friendly version of the support vector machine (SVM), which is useful to implement its feed-forward phase on limited-resources devices such as field programmable gate arrays (FPGAs) or microcontrollers, where a floating-point unit is seldom available. Our proposal is tested on a machine-vision benchmark dataset for automotive applications. A Hardware-friendly Support Vector Machine for Embedded Automotive Applications D Anguita A Ghio S Pischiutta S Ridella doi:10.1109/IJCNN.2007.4371156 Neural Networks, 2007. IJCNN 2007. International Joint Conference on (2007), pp. 1360-1364. 2008-06-25T15:28:21-00:00 2007 Neural Networks, 2007. IJCNN 2007. International Joint Conference on 1360 1364 fixedpoint svm http://www.citeulike.org/user/mmuecke/article/2926145 <i>Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on, Vol. 2 (2005), pp. 681-684 vol. 2.</i><br /><br />We apply here a probabilistic method to predict the effect of quantizing the parameters of a support vector machine with Gaussian kernel. Thanks to the particular structure of the SVM, the dependency of the output from the quantization noise can be predicted with good accuracy, and a simple closed-form formula can be derived, without imposing any hard-to-verify assumption. The effect of quantization on support vector machines with Gaussian kernel D Anguita G Bozza Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on, Vol. 2 (2005), pp. 681-684 vol. 2. 2008-06-25T15:27:04-00:00 2005 Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on 2 681 684 vol. 2 error_analysis svm http://www.citeulike.org/user/mmuecke/article/2925857 <i>Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on (2006), pp. 1-6.</i><br /><br />This paper describes preliminary performance results of a reconfigurable hardware implementation of a support vector machine classifier, aimed at brain-computer interface applications, which require real-time decision making in a portable device. The main constraint of the design was that it could perform a classification decision within the time span of an evoked potential recording epoch of 300 ms, which was readily achieved for moderate-sized support vector sets. Regardless of its fixed-point implementation, the FPGA-based model achieves equivalent classification accuracies to those of its software-based, floating-point counterparts An FPGA Implementation of Linear Kernel Support Vector Machines Omar Pina-Ramirez Raquel Valdes-Cristerna Oscar Yanez-Suarez doi:10.1109/RECONF.2006.307784 Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on (2006), pp. 1-6. 2008-06-25T12:45:01-00:00 2006 Reconfigurable Computing and FPGA's, 2006. ReConFig 2006. IEEE International Conference on 1 6 fixedpoint svm http://www.citeulike.org/user/mmuecke/article/2925854 <i>Instrumentation and Measurement, IEEE Transactions on, Vol. 56, No. 1. (2007), pp. 39-44.</i><br /><br />In this paper, we propose an efficient implementation of support vector machines (SVMs) on a low-power and low-cost 8-bit microcontroller. The proposed solution can be advantageously used to implement smart sensors and sensor networks for intelligent data analysis and pervasive computing. A new model selection algorithm that allows fitting the resource constraints imposed by the hardware architecture is proposed. Moreover, the performance of an optimized implementation which exploits the CORDIC algorithm is detailed and discussed Low-Power and Low-Cost Implementation of SVMs for Smart Sensors A Boni F Pianegiani D Petri doi:10.1109/TIM.2006.887319 Instrumentation and Measurement, IEEE Transactions on, Vol. 56, No. 1. (2007), pp. 39-44. 2008-06-25T12:43:33-00:00 2007 Instrumentation and Measurement, IEEE Transactions on 56 1 39 44 svm http://www.citeulike.org/user/mmuecke/article/2925845 <i>Digital System Design, 2004. DSD 2004. Euromicro Symposium on (2004), pp. 254-261.</i><br /><br />In this paper we present an analysis of the minimal hardware precision required to implement support vector machine (SVM) classification within a logarithmic number system architecture. Support vector machines are fast emerging as a powerful machine-learning tool for pattern recognition, decision-making and classification. Logarithmic number systems (LNS) utilize the property of logarithmic compression for numerical operations. Within the logarithmic domain, multiplication and division can be treated simply as addition or subtraction. Hardware computation of these operations is significantly faster with reduced complexity. Leveraging the inherent properties of LNS, we are able to achieve significant savings over double-precision floating point in an implementation of a SVM classification algorithm. Finite precision analysis of support vector machine classification in logarithmic number systems FM Khan MG Arnold WM Pottenger doi:10.1109/DSD.2004.1333285 Digital System Design, 2004. DSD 2004. Euromicro Symposium on (2004), pp. 254-261. 2008-06-25T12:37:38-00:00 2004 Digital System Design, 2004. DSD 2004. Euromicro Symposium on 254 261 error_analysis mixed_precision svm http://www.citeulike.org/user/mmuecke/article/2925844 <i>Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on, Vol. 5 (2005), pp. 2867-2872 vol. 5.</i><br /><br />The availability of powerful field programmable gate arrays (FPGA) has been exploited for their ability to rovide hardware solutions for many application areas, resulting in high-performance systems that can operate in real time by operating in parallel. The support vector machine computational paradigm can be cast as a collection of multiple streams operating in parallel on one such FPGA. This paper presents a parallel architecture that implements an SVM on a Xilinx FPGA. The results obtained by using this architecture for a complex pattern classification from high-energy physics involving thousands of patterns are reported and discussed, comparing the performance obtained by this architectural solution to that of a simpler sequential architecture. A reconfigurable parallel architecture for SVM classification I Biasi A Boni A Zorat doi:10.1109/IJCNN.2005.1556380 Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on, Vol. 5 (2005), pp. 2867-2872 vol. 5. 2008-06-25T12:36:53-00:00 2005 Neural Networks, 2005. IJCNN '05. Proceedings. 2005 IEEE International Joint Conference on 5 2867 2872 vol. 5 svm http://www.citeulike.org/user/mmuecke/article/2906757 <i>(1996), pp. 93-97.</i> Preparation for research: instruction in interpreting and evaluating research Alan Fekete doi:10.1145/236452.236516 (1996), pp. 93-97. 2008-06-19T08:09:20-00:00 1996 93 97 ACM scientific_publishing teaching http://www.citeulike.org/user/mmuecke/article/2906740 <i>Computer, Vol. 23, No. 4. (April 1990), pp. 65-71.</i> The Task of the Referee Alan Smith Computer, Vol. 23, No. 4. (April 1990), pp. 65-71. 2008-06-19T07:51:00-00:00 1990 Computer 0018-9162 23 4 65 71 IEEE Computer Society Press scientific_publishing http://www.citeulike.org/user/mmuecke/article/2898775 <i>(2008), pp. 79-88.</i> A domain specific interconnect for reconfigurable computing Sanjay Rajopadhye Gautam Gupta Lakshminarayanan Renganarayana doi:10.1145/1375657.1375669 (2008), pp. 79-88. 2008-06-16T14:23:25-00:00 2008 79 88 ACM reconfigurable_computing http://www.citeulike.org/user/mmuecke/article/1475012 <i>Pattern Analysis and Machine Intelligence, IEEE Transactions on, Vol. 29, No. 7. (2007), pp. 1180-1193.</i><br /><br />Many vision problems can be formulated as minimization of appropriate energy functionals. These energy functionals are usually minimized, based on the calculus of variations (Euler-Lagrange equation). Once the Euler-Lagrange equation has been determined, it needs to be discretized in order to implement it on a digital computer. This is not a trivial task and, is moreover, error-prone. In this paper, we propose a flexible alternative. We discretize the energy functional and, subsequently, apply the mathematical concept of algorithmic differentiation to directly derive algorithms that implement the energy functional's derivatives. This approach has several advantages: First, the computed derivatives are exact with respect to the implementation of the energy functional. Second, it is basically straightforward to compute second-order derivatives and, thus, the Hessian matrix of the energy functional. Third, algorithmic differentiation is a process which can be automated. We demonstrate this novel approach on three representative vision problems (namely, denoising, segmentation, and stereo) and show that state-of-the-art results are obtained with little effort. Algorithmic Differentiation: Application to Variational Problems in Computer Vision Thomas Pock Michael Pock Horst Bischof doi:10.1109/TPAMI.2007.1044 Pattern Analysis and Machine Intelligence, IEEE Transactions on, Vol. 29, No. 7. (2007), pp. 1180-1193. 2007-07-23T12:16:48-00:00 2007 Pattern Analysis and Machine Intelligence, IEEE Transactions on 29 7 1180 1193 gpu image_processing http://www.citeulike.org/user/mmuecke/article/2889540 <i>Artificial Intelligence and Symbolic Mathematical Computation (1996), pp. 144-159.</i><br /><br />This paper is an attempt to address the processing of non-linear numerical constraints over the Reals by combining three different methods: local consistency techniques, symbolic rewriting and interval methods. To formalize this combination, we define a generic two-step constraint processing technique based on an extension of the Constraint Satisfaction Problem, called Extended Constraint Satisfaction Problem (ECSP). The first step is a rewriting step, in which the initial ECSP is symbolically transformed. The second step, called approximation step, is based on a local consistency notion, called weak arc-consistency, defined over ECSPs in terms of fixed point of contractant monotone operators. This notion is shown to generalize previous local consistency concepts defined over finite domains (arc-consistency) or infinite subsets of the Reals (arc B-consistency and interval, hull and box-consistency). A filtering algorithm, derived from AC-3, is given and is shown to be correct, confluent and to terminate. This framework is illustrated by the combination of Gröbner Bases computations and Interval Newton methods. The computation of Gröbner Bases for subsets of the initial set of constraints is used as a rewriting step and operators based on Interval Newton methods are used together with enumeration techniques to achieve weak arc-consistency on the modified ECSP. Experimental results from a prototype are presented, as well as comparisons with other systems. Combining local consistency, symbolic rewriting and interval methods Frédéric Benhamou Laurent Granvilliers doi:10.1007/3-540-61732-9_55 Artificial Intelligence and Symbolic Mathematical Computation (1996), pp. 144-159. 2008-06-12T15:14:02-00:00 1996 Artificial Intelligence and Symbolic Mathematical Computation 144 159 interval_arithmetic term_rewriting http://www.citeulike.org/user/mmuecke/article/2887024 <i>(2006)</i> Exploiting the performance of 32 bit floating point arithmetic in obtaining 64 bit accuracy (revisiting iterative refinement for linear systems) Julie Langou Julien Langou Piotr Luszczek Jakub Kurzak Alfredo Buttari Jack Dongarra doi:10.1145/1188455.1188573 (2006) 2008-06-12T11:19:53-00:00 2006 ACM floating_point mixed_precision http://www.citeulike.org/user/mmuecke/article/2886899 <i>International Journal of Parallel, Emergent and Distributed Systems, Vol. 22, No. 4. (2007), pp. 221-256.</i><br /><br />In this survey paper, we compare native double precision solvers with emulated- and mixed-precision solvers of linear systems of equations as they typically arise in finite element discretisations. The emulation utilises two single float numbers to achieve higher precision, while the mixed precision iterative refinement computes residuals and updates the solution vector in double precision but solves the residual systems in single precision. Both techniques have been known since the 1960s, but little attention has been devoted to their performance aspects. Motivated by changing paradigms in processor technology and the emergence of highly-parallel devices with outstanding single float performance, we adapt the emulation and mixed precision techniques to coupled hardware configurations, where the parallel devices serve as scientific co-processors. The performance advantages are examined with respect to speedups over a native double precision implementation (time aspect) and reduced area requirements for a chip (space aspect). The paper begins with an overview of the theoretical background, algorithmic approaches and suitable hardware architectures. We then employ several conjugate gradient (CG) and multigrid solvers and study their behaviour for different parameter settings of the iterative refinement technique. Concrete speedup factors are evaluated on the coupled hardware configuration of a general-purpose CPU and a graphics processor. The dual performance aspect of potential area savings is assessed on a field programmable gate array (FPGA). In the last part, we test the applicability of the proposed mixed precision schemes with ill-conditioned matrices. We conclude that the mixed precision approach works very well with the parallel co-processors gaining speedup factors of four to five, and area savings of three to four, while maintaining the same accuracy as a reference solver executing everything in double precision. Performance and accuracy of hardware-oriented native-, emulated- and mixed-precision solvers in FEM simulations Dominik Göddeke Robert Strzodka Stefan Turek doi:10.1080/17445760601122076 International Journal of Parallel, Emergent and Distributed Systems, Vol. 22, No. 4. (2007), pp. 221-256. 2008-06-12T10:03:59-00:00 2007 International Journal of Parallel, Emergent and Distributed Systems 22 4 221 256 Taylor & Francis floating_point mixed_precision http://www.citeulike.org/user/mmuecke/article/2882882 <i>Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (2005), pp. 5154-5157 Vol. 5.</i><br /><br />Support vector machines are emerging as a powerful machine-learning tool. Logarithmic number systems (LNS) utilize the property of logarithmic compression for numerical operations. We present an implementation of a digital support vector machine (SVM) classifier using LNS in which, when compared with other implementations, considerable hardware savings are achieved with no significant loss in classification accuracy. Hardware-based support vector machine classification in logarithmic number systems FM Khan MG Arnold WM Pottenger doi:10.1109/ISCAS.2005.1465795 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (2005), pp. 5154-5157 Vol. 5. 2008-06-11T15:02:11-00:00 2005 Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on 5154 5157 Vol. 5 svm http://www.citeulike.org/user/mmuecke/article/2878971 <i>(2007), pp. 1-12.</i> The Cray BlackWidow: a highly scalable vector multiprocessor Dennis Abts Abdulla Bataineh Steve Scott Greg Faanes Jim Schwarzmeier Eric Lundberg Tim Johnson Mike Bye Gerald Schwoerer doi:10.1145/1362622.1362646 (2007), pp. 1-12. 2008-06-10T09:35:28-00:00 2007 1 12 ACM computer_architecture high-performance_computing http://www.citeulike.org/user/mmuecke/article/2878968 <i>(2007), pp. 1-11.</i> GRAPE-DR: 2-Pflops massively-parallel computer with 512-core, 512-Gflops processor chips for scientific computing Junichiro Makino Kei Hiraki Mary Inaba doi:10.1145/1362622.1362647 (2007), pp. 1-11. 2008-06-10T09:31:53-00:00 2007 1 11 ACM computer_architecture high-performance_computing molecular_dynamics http://www.citeulike.org/user/mmuecke/article/2878960 <i>(2007), pp. 1-12.</i> A case for low-complexity MP architectures H\aakan Zeffer Erik Hagersten doi:10.1145/1362622.1362648 (2007), pp. 1-12. 2008-06-10T09:29:20-00:00 2007 1 12 ACM architecture_comparison computer_architecture trends http://www.citeulike.org/user/mmuecke/article/2878802 <i>(2008)</i> Multi-Sensor Multi-Level Information Fusion on Embedded Systems Andreas Klausner (2008) 2008-06-10T08:06:19-00:00 2008 svm http://www.citeulike.org/user/mmuecke/article/740823 <i>ACM Comput. Surv., Vol. 28, No. 4. (December 1996), pp. 626-643.</i> Formal methods: state of the art and future directions Edmund Clarke Jeannette Wing doi:10.1145/242223.242257 ACM Comput. Surv., Vol. 28, No. 4. (December 1996), pp. 626-643. 2006-07-05T20:35:45-00:00 1996 ACM Comput. Surv. 0360-0300 28 4 626 643 ACM Press survey term_rewriting verification http://www.citeulike.org/user/mmuecke/article/333539 <i>(2005), pp. 168-179.</i> High-level views on low-level representations Iavor Diatchki Mark Jones Rebekah Leslie doi:10.1145/1086365.1086387 (2005), pp. 168-179. 2005-09-28T08:30:09-00:00 2005 168 179 ACM Press functional language_design vlsi_design http://www.citeulike.org/user/mmuecke/article/2869457 <i>ACM Trans. Math. Softw., Vol. 33, No. 2. (June 2007)</i> MPFR: A multiple-precision binary floating-point library with correct rounding Laurent Fousse Guillaume Hanrot Vincent Lefèvre Patrick Pélissier Paul Zimmermann doi:10.1145/1236463.1236468 ACM Trans. Math. Softw., Vol. 33, No. 2. (June 2007) 2008-06-06T13:52:58-00:00 2007 ACM Trans. Math. Softw. 0098-3500 33 2 ACM floating_point mixed_precision http://www.citeulike.org/user/mmuecke/article/2869447 <i>(2001), pp. 277-282.</i> Using symbolic algebra in algorithmic level DSP synthesis Armita Peymandoust Giovanni De Micheli doi:10.1145/378239.378485 (2001), pp. 277-282. 2008-06-06T13:45:38-00:00 2001 277 282 ACM high_level_synthesis term_rewriting http://www.citeulike.org/user/mmuecke/article/2869308 <i>(2001), pp. 209-216.</i> Hybrid system for multi-language and multi-environment generation of numerical codes Joze Korelc doi:10.1145/384101.384130 (2001), pp. 209-216. 2008-06-06T12:20:33-00:00 2001 209 216 ACM compiler_design language_design term_rewriting http://www.citeulike.org/user/mmuecke/article/2869304 <i>(2001), pp. 32-37.</i> Maple's evaluation process as constraint contextual rewriting Alessandro Armando Clemens Ballarin doi:10.1145/384101.384107 (2001), pp. 32-37. 2008-06-06T12:17:55-00:00 2001 32 37 ACM term_rewriting http://www.citeulike.org/user/mmuecke/article/2399069 <i>EURASIP J. Embedded Syst., Vol. 2006, No. 1. (January 2006), pp. 21-21.</i> Efficient design methods for embedded communication systems M Holzer B Knerr P Belanovic M Rupp doi:10.1155/ES/2006/64913 EURASIP J. Embedded Syst., Vol. 2006, No. 1. (January 2006), pp. 21-21. 2008-02-19T14:54:25-00:00 2006 EURASIP J. Embedded Syst. 1687-3955 2006 1 21 21 Hindawi Publishing Corp. electronics_design_automation fixedpoint high_level_synthesis survey http://www.citeulike.org/user/mmuecke/article/2864354 <i>Computing in Science & Engineering, Vol. 2, No. 4. (2000), pp. 58-68.</i><br /><br />How sensitive to rounding errors are the results generated from a particular code running on a particular machine applied to a particular input? Monte Carlo arithmetic illustrates the potential for tools to support new kinds of a posteriori round-off error analysis Monte Carlo arithmetic: how to gamble with floating point and win DS Parker B Pierce PR Eggert doi:10.1109/5992.852391 Computing in Science & Engineering, Vol. 2, No. 4. (2000), pp. 58-68. 2008-06-05T10:47:44-00:00 2000 Computing in Science & Engineering 2 4 58 68 error_analysis floating_point http://www.citeulike.org/user/mmuecke/article/2861341 <i>Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on, Vol. 2 (2003), pp. II-561-4 vol.2.</i><br /><br />During the development of floating-point signal processing systems, an efficient error analysis method is needed to guarantee the output quality. We present a novel approach to floating-point error bound analysis based on affine arithmetic. The proposed method not only provides a tighter bound than the conventional approach, but also is applicable to any arithmetic operation. The error estimation accuracy is evaluated across several different applications which cover linear operations, nonlinear operations, and feedback systems. The accuracy decreases with the depth of computation path and also is affected by the linearity of the floating-point operations. Floating-point error analysis based on affine arithmetic CF Fang Tsuhan Chen RA Rutenbar doi:10.1109/ICASSP.2003.1202428 Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on, Vol. 2 (2003), pp. II-561-4 vol.2. 2008-06-04T14:52:29-00:00 2003 Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on 2 II 561-4 vol.2 error_analysis floating_point http://www.citeulike.org/user/mmuecke/article/2860622 <i>ACM Trans. Math. Softw., Vol. 27, No. 1. (March 2001), pp. 92-118.</i><br /><br />This paper introduces a precision- and range-independent tool for testing the compliance of hardware or software implementations of (multiprecision) floating-point arithmetic with the principles of the IEEE standards 754 and 854. The tool consists of a driver program, offering many options to test only specific aspects of the IEEE standards, and a large set of test vectors, encoded in a precision-independent syntax to allow the testing of basic and extended hardware formats as well as multiprecision floating-point implementations. The suite of test vectors stems on one hand from the integration and fully precision- and range-independent generalization of existing hardware test sets, and on the other hand from the systematic testing of exact rounding for all combinations of round and sticky bits that can occur. The former constitutes only 50% of the resulting test set. In the latter we especially focus on hard-to-round cases. In addition, the test suite implicitly tests properties of floating-point operations, following the idea of Paranoia, and it reports which of the three IEEE-compliant underflow mechanisms is used by the floating-point implementation under consideration. We also chech whether that underflow mechanism is used consistently. The tool is backward compatible with the UCBTEST package and with Coonen's test syntax. A precision- and range-independent tool for testing floating-point arithmetric I: basic operations, square root, and remainder Bridgitte Verdonk Annie Cuyt Dennis Verschaeren doi:10.1145/382043.382404 ACM Trans. Math. Softw., Vol. 27, No. 1. (March 2001), pp. 92-118. 2008-06-04T09:41:52-00:00 2001 ACM Trans. Math. Softw. 0098-3500 27 1 92 118 ACM floating_point http://www.citeulike.org/user/mmuecke/article/2514901 <i>Int. J. High Perform. Comput. Appl., Vol. 21, No. 4. (November 2007), pp. 457-466.</i> Mixed Precision Iterative Refinement Techniques for the Solution of Dense Linear Systems Alfredo Buttari Jack Dongarra Julie Langou Julien Langou Piotr Luszczek Jakub Kurzak doi:10.1177/1094342007084026 Int. J. High Perform. Comput. Appl., Vol. 21, No. 4. (November 2007), pp. 457-466. 2008-03-11T13:25:50-00:00 2007 Int. J. High Perform. Comput. Appl. 1094-3420 21 4 457 466 Sage Publications, Inc. cell_cpu floating_point mixed_precision http://www.citeulike.org/user/mmuecke/article/2858543 <i>XCell (2008)</i> Developing FPGA Coprocessors for Performance-Accelerated Spacecraft Image Processing Paula Pingree Lucas Scharenbroich Thomas Werne David Pellerin XCell (2008) 2008-06-03T08:43:31-00:00 2008 XCell electronics_design_automation fpga reconfigurable_computing svm http://www.citeulike.org/user/mmuecke/article/2857390 <i>Cluster Computing and the Grid, 2008. CCGRID '08. 8th IEEE International Symposium on (2008), pp. 130-137.</i><br /><br />The advances in multicore technology and modern interconnects is rapidly accelerating the number of cores deployed in today's commodity clusters. A majority of parallel applications written in MPI employ collective operations in their communication kernels. Optimization of these operations on the multicore platforms is the key to obtaining good performance speed-ups. However, designing these operations on the modern multicores is a non-trivial task. Modern multicores such as Intel's Clovertown and AMD's Opteron feature various architectural attributes resulting in interesting ramifications. For example, Clovertown deploys shared L2 caches for a pair of cores whereas in Opteron, L2 caches are exclusive to a core. Understanding the impact of these architectures on communication performance is crucial to designing efficient collective algorithms. In this paper, we systematically evaluate these architectures and use these insights to develop efficient collective operations such as MPI_Bcast, MPI_Allgather, MPI_Allreduce and MPI_Alltoall. Further, we characterize the behavior of these collective algorithms on multicores especially when concurrent network and intra-node communications occur. We also evaluate the benefits of the proposed intra-node MPI_Allreduce over Opteron multicores and compare it with Intel Clovertown systems. The optimizations proposed in this paper reduce the latency of MPI_Bcast and MPI_Allgather by 1.9 and 4.0 times, respectively on 512 cores. For MPI_Allreduce, our optimizations improve the performance by as much as 33&#x025; on the multicores. Further, we observe upto three times improvement in performance for matrix multiplication benchmark on 512 cores. MPI Collectives on Modern Multicore Clusters: Performance Optimizations and Communication Characteristics Amith Mamidala Rahul Kumar Debraj De DK Panda doi:10.1109/CCGRID.2008.87 Cluster Computing and the Grid, 2008. CCGRID '08. 8th IEEE International Symposium on (2008), pp. 130-137. 2008-06-02T15:12:54-00:00 2008 Cluster Computing and the Grid, 2008. CCGRID '08. 8th IEEE International Symposium on 130 137 communication_algorithms infiniband mpi performance_analysis http://www.citeulike.org/user/mmuecke/article/2837205 <i>(1990)</i> NASA Guide to Grammar, Punctuation, and Capitalization: A Handbook for Technical Writers and Editors Mary Mccaskill (1990) 2008-05-27T10:49:43-00:00 1990 scientific_publishing http://www.citeulike.org/user/mmuecke/article/1179116 <i>Computer, Vol. 40, No. 3. (2007), pp. 66-73.</i><br /><br />A field-programmable gate array implementation of a molecular dynamics simulation method reduces the microprocessor time-to-solution by a factor of three while using only high-level languages. The application speedup on FPGA devices increases with the problem size. The authors use a performance model to analyze the potential of simulating large-scale biological systems faster than many cluster-based supercomputing platforms. Using FPGA Devices to Accelerate Biomolecular Simulations Sadaf Alam Pratul Agarwal Melissa Smith Jeffrey Vetter David Caliga Computer, Vol. 40, No. 3. (2007), pp. 66-73. 2007-03-21T14:21:59-00:00 2007 Computer 40 3 66 73 fpgasupercomputing high-performance_computing molecular_dynamics http://www.citeulike.org/user/mmuecke/article/1179110 <i>Computer, Vol. 40, No. 3. (2007), pp. 28-37.</i><br /><br />Unlocking the potential of field-programmable gate arrays requires compilers that translate algorithmic high-level language code into hardware circuits. The Trident open source compiler translates C code to a hardware circuit description, providing designers with extreme flexibility in prototyping reconfigurable supercomputers. Trident: From High-Level Language to Hardware Circuitry Justin Tripp Maya Gokhale Kristopher Peterson Computer, Vol. 40, No. 3. (2007), pp. 28-37. 2007-03-21T14:17:39-00:00 2007 Computer 40 3 28 37 electronics_design_automation fpga high_level_synthesis http://www.citeulike.org/user/mmuecke/article/1405131 <i>International Journal of Parallel Programming, Vol. 35, No. 3. (June 2007), pp. 263-298.</i><br /><br />In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end scientific computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key numerical kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. Next, we validate our model by comparing results against published hardware data, as well as our own Cell blade implementations. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different kernel implementations and demonstrates a simple and effective programming model for Cell’s unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency. Scientific Computing Kernels on the Cell Processor Samuel Williams John Shalf Leonid Oliker Shoaib Kamil Parry Husbands Katherine Yelick doi:10.1007/s10766-007-0034-5 International Journal of Parallel Programming, Vol. 35, No. 3. (June 2007), pp. 263-298. 2007-06-22T19:15:35-00:00 2007 International Journal of Parallel Programming 35 3 263 298 cell_cpu floating_point high-performance_computing http://www.citeulike.org/user/mmuecke/article/2833953 <i>Computing in Science & Engineering, Vol. 9, No. 5. (2007), pp. 70-77.</i><br /><br />High-performance reconfigurable computing combines the advantages of the coarse-grain parallel processing provided in conventional multiprocessor systems with the fine-grain parallel processing available in field-programmable gate arrays. Accelerating Scientific Applications with Reconfigurable Computing: Getting Started VV Kindratenko CP Steffen RJ Brunner doi:10.1109/MCSE.2007.91 Computing in Science & Engineering, Vol. 9, No. 5. (2007), pp. 70-77. 2008-05-26T12:14:42-00:00 2007 Computing in Science & Engineering 9 5 70 77 high-performance_computing reconfigurable_computing http://www.citeulike.org/user/mmuecke/article/1179114 <i>Computer, Vol. 40, No. 3. (2007), pp. 58-64.</i><br /><br />Using a high-level-language to hardware-description-language compiler and some novel architectures and algorithms to map two well-known double-precision floating-point sparse matrix iterative-linear-equation solvers--the Jacobi and conjugate gradient methods--onto a reconfigurable computer achieves more than a twofold speedup over software. Sparse Matrix Computations on Reconfigurable Hardware Viktor Prasanna Gerald Morris doi:10.1109/MC.2007.103 Computer, Vol. 40, No. 3. (2007), pp. 58-64. 2007-03-21T14:21:11-00:00 2007 Computer 40 3 58 64 floating_point high_level_synthesis high-performance_computing reconfigurable_computing sparse_matrix http://www.citeulike.org/user/mmuecke/article/595170 <i>Reliable Computing, Vol. 12, No. 3. (June 2006), pp. 225-237.</i> Hardware Support for Interval Arithmetic Kirchner Reinhard Kulisch Ulrich doi:10.1007/s11155-006-7220-9 Reliable Computing, Vol. 12, No. 3. (June 2006), pp. 225-237. 2006-04-22T16:04:53-00:00 2006 Reliable Computing 1385-3139 12 3 225 237 Springer floating_point interval_arithmetic vlsi_design http://www.citeulike.org/user/mmuecke/article/2818440 <i>(20 November 2002)</i><br /><br />The book deals with computer arithmetic in a more general sense than usual. Advanced computer arithmetic requires that all computer approximations of arithmetic operations – in particular those in the usual vector and matrix spaces – differ from the correct result by at most one rounding. The implementation of advanced computer arithmetic by fast hardware is examined in the book. The new expanded computational capability is gained at modest cost. It increases both the speed of a computation and the accuracy of the computed result. With it fast multiple precision arithmetic can be easily provided. All this strongly supports the case for implementing advanced computer arithmetic on every CPU. The book also shows that on superscalar processors interval operations can be made as fast as simple floating-point operations with only very modest additional hardware costs. Advanced Arithmetic for the Digital Computer Ulrich Kulisch (20 November 2002) 2008-05-21T07:29:03-00:00 2002 Springer book computer_architecture floating_point interval_arithmetic http://www.citeulike.org/user/mmuecke/article/2774707 <i>SIGMETRICS Perform. Eval. Rev., Vol. 35, No. 4. (March 2008), pp. 62-71.</i> Evaluating the performance of single and multiple core processors with PCMARK\textregistered05 and benchmark analysis Fadi Sibai doi:10.1145/1364644.1364647 SIGMETRICS Perform. Eval. Rev., Vol. 35, No. 4. (March 2008), pp. 62-71. 2008-05-09T08:11:22-00:00 2008 SIGMETRICS Perform. Eval. Rev. 0163-5999 35 4 62 71 ACM computer_architecture performance_analysis