Thu, 21 Aug 2008 00:46:09 BST CiteULike: mmuecke's reconfigurable_platforms http://www.citeulike.org/user/mmuecke/tag/reconfigurable_platforms CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/mmuecke/article/3095840 <i>Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on (2007), pp. 301-310.</i><br /><br />We describe the FPGA HPC Alliance's parallel toolkit (PTK), an initial step towards the standardization of high-level configuration and APIs for high-performance reconfigurable computing (HPRC). We discuss the motivation and challenges of reaping the performance benefits of FPGAs for memory-bound HPC codes and describe the approach we have taken on the FHPCA supercomputer Maxwell. The FPGA High-Performance Computing Alliance Parallel Toolkit R Baxter S Booth M Bull G Cawood J Perry M Parsons A Simpson A Trew A Mccormick G Smart R Smart A Cantle R Chamberlain G Genest doi:10.1109/AHS.2007.104 Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on (2007), pp. 301-310. 2008-08-07T12:42:37-00:00 2007 Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on 301 310 middle_ware reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/3094062 <i>Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on (2007), pp. 287-294.</i><br /><br />We present the initial results from the FHPCA Supercomputer project at the University of Edinburgh. The project has successfully built a general-purpose 64 FPGA computer and ported to it three demonstration applications from the oil, medical and finance sectors. This paper describes in brief the machine itself - Maxwell - its hardware and software environment and presents very early benchmark results from runs of the demonstrators. Maxwell - a 64 FPGA Supercomputer R Baxter S Booth M Bull G Cawood J Perry M Parsons A Simpson A Trew A Mccormick G Smart R Smart A Cantle R Chamberlain G Genest doi:10.1109/AHS.2007.71 Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on (2007), pp. 287-294. 2008-08-07T07:25:15-00:00 2007 Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on 287 294 fpgasupercomputing reconfigurable_computing reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/2947829 <i>Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 91-97.</i> Anton, a special-purpose machine for molecular dynamics simulation David Shaw Martin Deneroff Ron Dror Jeffrey Kuskin Richard Larson John Salmon Cliff Young Brannon Batson Kevin Bowers Jack Chao Michael Eastwood Joseph Gagliardo JP Grossman Richard Ho Douglas Lerardi István Kolossváry John Klepeis Timothy Layman Christine Mcleavey Mark Moraes Rolf Mueller Edward Priest Yibing Shan Jochen Spengler Michael Theobald Brian Towles Stanley Wang doi:10.1145/1364782.1364802 Commun. ACM, Vol. 51, No. 7. (July 2008), pp. 91-97. 2008-07-01T12:30:10-00:00 2008 Commun. ACM 0001-0782 51 7 91 97 ACM molecular_dynamics reconfigurable_platforms vlsi_design http://www.citeulike.org/user/mmuecke/article/2648416 <i>(2005), pp. 107-117.</i> An FPGA-based VLIW processor with custom hardware execution Alex Jones Raymond Hoare Dara Kusic Joshua Fazekas John Foster doi:10.1145/1046192.1046207 (2005), pp. 107-117. 2008-04-10T08:44:58-00:00 2005 107 117 ACM computer_architecture electronics_design_automation fpga high_level_synthesis reconfigurable_computing reconfigurable_platforms vhdl http://www.citeulike.org/user/mmuecke/article/2314064 <i>Configurable Computing: Technology and Applications, Vol. 3526, No. 1. (1998), pp. 124-133.</i><br /><br />Reconfigurable computing devices are emerging as a viable alternative to fixed-function components and programmable processors. To expand our knowledge of the role and optimization of these devices, it is increasingly imperative for us to compare implementations of tasks and subroutines across this wide spectrum of implementation options. The fact that most processors, FPGAs, ASICs, and memories are fabricated in a uniform technology medium, CMOS VLSI, where area scaling is moderately well understood eases our comparison task. Nonetheless, the rapid pace of technology, limited device size selection, and economic artifacts complicate the picture. In this paper, we look at the task of comparing computing machines, reviewing normalization techniques and many important issues which arise during comparisons. This paper includes examples intended to underscore the methodology and comparison issues, but does not attempt to make definitive conclusions about the merits of the technology alternatives from the small sample set. The immediate intent of this work is to help designers faced with tradeoffs between technological alternatives. The longer term intent is to help the community collect and analyze the broad-based data needed to better understand the range of available computing options. Comparing computing machines Andre Dehon doi:10.1117/12.327025 Configurable Computing: Technology and Applications, Vol. 3526, No. 1. (1998), pp. 124-133. 2008-01-31T13:19:17-00:00 1998 Configurable Computing: Technology and Applications 3526 1 124 133 SPIE architecture_comparison computer_architecture fpga reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/337765 <i>Computers and Digital Techniques, IEE Proceedings-, Vol. 152, No. 2. (2005), pp. 193-207.</i><br /><br />Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications. Reconfigurable computing: architectures and design methods TJ Todman GA Constantinides SJE Wilton O Mencer W Luk PYK Cheung doi:10.1049/ip-cdt:20045086 Computers and Digital Techniques, IEE Proceedings-, Vol. 152, No. 2. (2005), pp. 193-207. 2005-09-30T21:41:05-00:00 2005 Computers and Digital Techniques, IEE Proceedings- 152 2 193 207 reconfigurable_computing reconfigurable_platforms survey http://www.citeulike.org/user/mmuecke/article/1965652 <i>(14 December 2005)</i><br /><br /><P>This volume is unique: the first comprehensive exposition of the exciting new field of Reconfigurable Computing with FPGAs. By mapping algorithms directly into programmable logic, FPGA accelerators offer and deliver 10X-100X performance increases over microprocessors for a large range of application domains. Reconfigurable computing is found in virtually every computing milieu, from satellites to supercomputers. By loading new hardware circuits onto the FPGA, or even modifying parts of the circuit during operation, reconfigurable computers achieve performance rivaling application-specific integrated circuits (ASICs), yet are built from commodity parts.</P> <P>The authors are among the originators of <STRONG>Reconfigurable Computing</STRONG> and are recognized leaders in the field. Drawing on their deep familiarity with RC, they survey every aspect of the field, from FPGA device architecture, reconfigurable systems architectures, programming languages and compilation tools to the application domains of signal processing, image processing, network security, bioinformatics, and supercomputing. Although citations to original sources are abundant, nevertheless, the book is accessible to the science and technology practitioner and student.</P> <P><STRONG>Reconfigurable Computing</STRONG> is of especially topical to computer science and engineering researchers as well as professionals in high performance computing and embedded computing.</P> Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays Maya Gokhale Paul Graham (14 December 2005) 2007-11-23T11:38:28-00:00 2005 Springer book fpgasupercomputing reconfigurable_computing reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/300038 <i>ACM Comput. Surv., Vol. 34, No. 2. (June 2002), pp. 171-210.</i> Reconfigurable computing: a survey of systems and software Katherine Compton Scott Hauck doi:10.1145/508352.508353 ACM Comput. Surv., Vol. 34, No. 2. (June 2002), pp. 171-210. 2005-08-21T12:52:24-00:00 2002 ACM Comput. Surv. 0360-0300 34 2 171 210 ACM Press fpga reconfigurable_computing reconfigurable_platforms survey trends http://www.citeulike.org/user/mmuecke/article/310767 <i>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 4, No. 1. (1996), pp. 56-69.</i><br /><br />Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field-programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAM's offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAM's, through the example of DECPeRLe-1, an experimental device built in 1992. PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in 1992. A technology shrink increases the performance gap between conventional processors and PAM's. By Noyce's law, we predict by how much the performance gap will widen with time Programmable active memories: reconfigurable systems come of age JE Vuillemin P Bertin D Roncin M Shand HH Touati P Boucard doi:10.1109/92.486081 Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 4, No. 1. (1996), pp. 56-69. 2005-09-02T14:20:53-00:00 1996 Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 4 1 56 69 fpgas_in_hep reconfigurable_computing reconfigurable_platforms trends http://www.citeulike.org/user/mmuecke/article/1236546 <i>(September 2005)</i> FPGA Dynamic Reconfiguration in ALICE and beyond Gerd Troeger (September 2005) 2007-04-19T09:24:50-00:00 2005 fpgas_in_hep reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/620598 <i>FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 175-184.</i><br /><br />JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard programming abstractions found in object-oriented languages. JHDL manages FPGA resources in a manner that is similar to the way object-oriented languages manage memory: circuits are treated as distinct objects and a circuit is configured onto a configurable computing machine (CCM) by invoking its constructor effectively “constructing ” an instance of the circuit onto the reconfigurable platform just as object instances are allocated in memory with conventional object-oriented languages. This approach of using object constructors/destructors to control the circuit lifetime on a CCM is a powerful technique that naturally leads to a dual simulation/execution environment where a designer can easily switch between either software simulation or hardware execution on a CCM with a single application description. Moreover JHDL supports dual hardware/software execution; parts of the application described using JHDL circuit constructs can be executed on the CCM while the remainder of the application the-GUI for example-can run on the CCM host. Based on an existing programming language (Java), JHDL requires no language extensions and can be used with any standard Java 1.1 distribution JHDL-an HDL for reconfigurable systems P Bellows B Hutchings FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 175-184. 2006-05-09T16:26:45-00:00 1998 FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on 175 184 hdl hdl_tool language_embedding open_source_eda reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/1141847 <i>Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 12, No. 4. (2004), pp. 420-436.</i><br /><br />This paper presents a high-level hardware description environment developed at Queen's University, Belfast, U.K., which aims to bridge the gap between application design and hardware description. The environment, called application-to-hardware (A2H), allows for efficient compilation of high-level application descriptions to field programmable gate array (FPGA) hardware in the form of EDIF netlist in seconds. A key concept in bridging the gap while retaining the hardware efficiency, is that of hardware skeletons. A hardware skeleton is a parameterized description of a task-specific architecture, to which the user can supply not only value parameters but also functions or even other skeletons. A skeleton contains built-in rules, which capture optimizations specific to the target hardware at the implementation phase. The rule-based logic programming language Prolog has been chosen as the base notation for the A2H environment. This paper includes descriptions of hardware skeletons abstractions in the particular context of image processing applications. The current implementation of our system targets Xilinx XC4000 and Virtex series FPGAs. From application descriptions to hardware in seconds: a logic-based approach to bridging the gap K Benkrid D Crookes Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 12, No. 4. (2004), pp. 420-436. 2007-03-05T14:55:57-00:00 2004 Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 12 4 420 436 dsl fpga hdl high_level_synthesis image_processing reconfigurable_platforms http://www.citeulike.org/user/mmuecke/article/1116460 <i>SIGOPS Oper. Syst. Rev., Vol. 40, No. 2. (April 2006), pp. 73-82.</i> SmartApps: middle-ware for adaptive applications on reconfigurable platforms Lawrence Rauchwerger Nancy Amato doi:10.1145/1131322.1131338 SIGOPS Oper. Syst. Rev., Vol. 40, No. 2. (April 2006), pp. 73-82. 2007-02-21T15:38:27-00:00 2006 SIGOPS Oper. Syst. Rev. 0163-5980 40 2 73 82 ACM Press fpga middle_ware reconfigurable_platforms