Thu, 21 Aug 2008 14:18:51 BST CiteULike: these_morel's microelectronics http://www.citeulike.org/user/these_morel/tag/microelectronics CiteULike.org en-gb Copyright © 2004-2008 citeulike.org http://www.citeulike.org/user/these_morel/article/2984947 <i>Technique de l'ingénieur, No. E2430. (February 2000)</i> Transistor MOS et sa technologie de fabrication Thomas Skotnicki Technique de l'ingénieur, No. E2430. (February 2000) 2008-07-10T12:35:54-00:00 2000 Technique de l'ingénieur E2430 cmos introduction microelectronics http://www.citeulike.org/user/these_morel/article/2692899 <i>(04 November 1981)</i><br /><br />This completely reorganized edition of the classic reference provides detailed information on the underlying physics and operational characteristics of all major bipolar, unipolar, special microwave, and optoelectronic devices. Integrates nearly 1,000 references to important original research papers and review articles, more than 650 high-quality technical illustrations, and 25 tables of material parameters for device analysis. Physics of Semiconductor Devices Simon Sze (04 November 1981) 2008-04-20T13:13:21-00:00 1981 Wiley-Interscience cmos introduction microelectronics http://www.citeulike.org/user/these_morel/article/2805144 <i>Electron Device Letters, IEEE, Vol. 18, No. 12. (1997), pp. 580-582.</i><br /><br />We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices A Gupta Peng Fang M Song Ming-Ren Lin D Wollesen K Chen C Hu doi:10.1109/55.644077 Electron Device Letters, IEEE, Vol. 18, No. 12. (1997), pp. 580-582. 2008-05-16T11:54:35-00:00 1997 Electron Device Letters, IEEE 18 12 580 582 introduction microelectronics polydepletion http://www.citeulike.org/user/these_morel/article/2804588 <i>Solid-State Electronics, Vol. 38, No. 11. (November 1995), pp. 1975-1977.</i> Polysilicon gate depletion effect on IC performance Kai Chen Mansun Chan Ping Ko Chenming Hu Jian-Hui Huang doi:10.1016/0038-1101(95)00108-6 Solid-State Electronics, Vol. 38, No. 11. (November 1995), pp. 1975-1977. 2008-05-16T07:06:26-00:00 1995 Solid-State Electronics 38 11 1975 1977 introduction microelectronics polydepletion http://www.citeulike.org/user/these_morel/article/2804551 <i>Electron Device Letters, IEEE, Vol. 10, No. 5. (1989), pp. 192-194.</i><br /><br />The <e1>C</e1>-<e1>V</e1> characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency <e1>C</e1>-<e1>V</e1> as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the <e1>G</e1>_m of NMOS transistors with 125-Å Gate oxide thickness Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology CY Lu JM Sung HC Kirsch SJ Hillenius TE Smith L Manchanda doi:10.1109/55.31717 Electron Device Letters, IEEE, Vol. 10, No. 5. (1989), pp. 192-194. 2008-05-16T06:33:18-00:00 1989 Electron Device Letters, IEEE 10 5 192 194 introduction microelectronics polydepletion http://www.citeulike.org/user/these_morel/article/2801898 <i>Electron Devices Meeting, 1996., International (1996), pp. 319-322.</i><br /><br />MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient for MOSFET scaling to 0.05 μm Gate oxide scaling limits and projection Chenming Hu doi:10.1109/IEDM.1996.553593 Electron Devices Meeting, 1996., International (1996), pp. 319-322. 2008-05-15T14:43:27-00:00 1996 Electron Devices Meeting, 1996., International 319 322 eot introduction microelectronics polydepletion tunneling http://www.citeulike.org/user/these_morel/article/2801881 <i>Electron Device Letters, IEEE, Vol. 23, No. 4. (2002), pp. 224-226.</i><br /><br />Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs Gate length dependent polysilicon depletion effects Chang-Hoon Choi PR Chidambaram R Khamankar CF Machala Zhiping Yu RW Dutton doi:10.1109/55.992846 Electron Device Letters, IEEE, Vol. 23, No. 4. (2002), pp. 224-226. 2008-05-15T14:34:33-00:00 2002 Electron Device Letters, IEEE 23 4 224 226 introduction microelectronics polydepletion http://www.citeulike.org/user/these_morel/article/2801499 <i>Proceedings of the IEEE, Vol. 89, No. 3. (2001), pp. 259-288.</i><br /><br />This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications Device scaling limits of Si MOSFETs and their application dependencies DJ Frank RH Dennard E Nowak PM Solomon Y Taur Hon-Sum Wong doi:10.1109/5.915374 Proceedings of the IEEE, Vol. 89, No. 3. (2001), pp. 259-288. 2008-05-15T12:26:04-00:00 2001 Proceedings of the IEEE 89 3 259 288 introduction microelectronics tunneling http://www.citeulike.org/user/these_morel/article/2797383 <i>Microelectronic Engineering, Vol. 82, No. 3-4. (December 2005), pp. 529-533.</i><br /><br />3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 [mu]m remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper. 3D Integration of CMOS transistors with ICV-SLID technology Robert Wieland Detlef Bonfert Armin Klumpp Reinhard Merkel Lars Nebrich Josef Weber Peter Ramm doi:10.1016/j.mee.2005.07.052 Microelectronic Engineering, Vol. 82, No. 3-4. (December 2005), pp. 529-533. 2008-05-14T10:37:32-00:00 2005 Microelectronic Engineering 82 3-4 529 533 3d-integration cmos microelectronics http://www.citeulike.org/user/these_morel/article/814762 <i>Electronics, Vol. 38, No. 8. (19 April 1965), pp. 82-85.</i> Cramming More Components Onto Integrated Circuits GE Moore doi:10.1109/JPROC.1998.658762 Electronics, Vol. 38, No. 8. (19 April 1965), pp. 82-85. 2006-08-24T03:27:44-00:00 1965 Electronics 38 8 82 85 microelectronics moores-law http://www.citeulike.org/user/these_morel/article/2729859 <i>IEEE Transactions on Electron Devices, Vol. 16, No. 2. (1969), pp. 236-236.</i> Insulated gate field effect transistor integrated circuits with silicon gates F Faggin T Klein L Vadasz IEEE Transactions on Electron Devices, Vol. 16, No. 2. (1969), pp. 236-236. 2008-04-28T12:29:03-00:00 1969 IEEE Transactions on Electron Devices 16 2 236 236 introduction microelectronics