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	Double precision floating-point arithmetic on FPGAs [My Copy] Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on (22 March 2004), pp. 352-358. by S. Paschalakis, P. Lee posted to fpga altera algorithm by mzabidi on 2009-10-23 17:00:08 as along with 1 person dcastro
	Parameterizable VLSI architectures for the full-search block-matching algorithm [My Copy] Circuits and Systems, IEEE Transactions on In Circuits and Systems, IEEE Transactions on, Vol. 36, No. 10. (1989), pp. 1309-1316. by L. de Vos, M. Stegherr posted to altera architecture blockmatching vision vlsi by mzabidi on 2008-09-24 00:35:48 as
	Dynamic Voltage Scaling for Commercial FPGAs [My Copy] Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology (2005), pp. 173-180. by C. T. Chow, L. S. M. Tsui, P. H. W. Leong, W. Luk, S. J. E. Wilton posted to altera architecture for_thesis fpga fpl_paper fpt_paper power power_estimation vlsi xilinx by nathalie on 2006-09-01 06:46:27 as along with 2 people reactgary ceegrs2
	Power-aware RAM Mapping for FPGA Embedded Memory Blocks [My Copy] In FPGA'06: Proceedings of the International Symposium on Field Programmable Gate Arrays (2006), pp. 189-198. by Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy posted to activity algorithms altera for_thesis fpga logic_synthesis memory power by nathalie on 2006-09-01 05:55:51 as along with 1 person ceegrs2
	Measuring the Gap Between FPGAs and ASICs [My Copy] In FPGA'06: Proceedings of the Internation Symposium on Field Programmable Gate Arrays (2006), pp. 21-30. by Ian Kuon, Jonathan Rose posted to altera area asic benchmarks for_thesis fpga leakage performance power xilinx by nathalie on 2006-09-01 05:24:19 as along with 4 people ericschung hannibal_08 ceegrs2 JonsonXP
	Fundamentals of Digital Logic with Verilog Design [My Copy] (20 August 2002) by Stephen Brown, Zvonko Vranesic posted to altera digital_logic for_thesis fpga by nathalie on 2006-08-29 06:31:28 as
	Directional and single-driver wires in FPGA interconnect [My Copy] Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (2004), pp. 41-48. by G. Lemieux, E. Lee, M. Tom, A. Yu posted to altera architecture for_thesis fpga interconnect routing xilinx by nathalie on 2006-08-28 04:10:16 as
	A verilog RTL synthesis tool for heterogeneous FPGAs [My Copy] Field Programmable Logic and Applications, 2005. International Conference on (2005), pp. 305-310. by P. Jamieson, J. Rose posted to altera arithmetic coarse_grained_architectures dsp for_thesis fpga fpl_paper logic_synthesis printed synthesis technology_mapping by nathalie on 2006-02-19 21:11:59 as
	A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure [My Copy] FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 226-234. by S. D. Haynes, P. Y. K. Cheung posted to altera architecture arithmetic embedded for_thesis fpga fpl_paper image_processing multiplier printed xilinx by nathalie on 2006-01-10 23:48:14 as
	The effect of LUT and cluster size on deep-submicron FPGA performance and density [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 12, No. 3. (2004), pp. 288-298. by E. Ahmed, J. Rose posted to altera architecture area clustering deep_submicron fpga lut performance printed by nathalie on 2005-12-20 05:12:58 as
	High-performance carry chains for FPGAs [My Copy] In FPGA '98: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays (1998), pp. 223-233. by Scott Hauck, Matthew M. Hosler, Thomas W. Fry posted to adder altera architecture arithmetic for_thesis fpga fpl_paper printed by nathalie on 2005-12-07 20:07:41 as
	Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs [My Copy] Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 (1999), pp. 191-194. by S. D. Haynes, A. B. Ferrari, P. Y. K. Cheung posted to altera architecture arithmetic for_thesis fpga fpl_paper multiplier printed xilinx by nathalie on 2005-06-22 06:32:37 as
	The stratix routing and logic architecture [My Copy] In FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays (2003), pp. 12-20. by David Lewis, Vaughn Betz, David Jefferson, et al.Andy Lee, Chris Lane, Paul Leventis, Sandy Marquardt, Cameron Mcclintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose posted to altera architecture fpga interconnect printed routing by nathalie on 2005-05-12 23:15:57 as
	The Stratix II logic and routing architecture [My Copy] In FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays (2005), pp. 14-20. by David Lewis, Elias Ahmed, Gregg Baeckler, et al.Vaughn Betz, Mark Bourgeault, David Cashman, David Galloway, Mike Hutton, Chris Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron Mcclintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose posted to altera architecture fpga interconnect printed routing by nathalie on 2005-05-12 22:18:40 as

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