Tag interconnect [82 articles] Export

Recent papers classified by the tag interconnect.

	An interconnect architecture for networking systems on chips [My Copy] Micro, IEEE, Vol. 22, No. 5. (10 December 2002), pp. 36-45. by F. Karim, A. Nguyen, S. Dey posted to thesis noc interconnect ieee_micro belinda by belin87 on 2009-09-29 16:40:30 as
	Chain: a delay-insensitive chip area interconnect [My Copy] Micro, IEEE, Vol. 22, No. 5. (10 December 2002), pp. 16-23. by J. Bainbridge, S. Furber posted to thesis interconnect ieee_micro belinda by belin87 on 2009-09-29 16:38:52 as
	Future microprocessors and off-chip SOP interconnect [My Copy] Advanced Packaging, IEEE Transactions on, Vol. 27, No. 2. (03 September 2004), pp. 301-303. by H. P. Hofstee posted to thesis interconnect belinda by belin87 on 2009-09-29 15:15:40 as
	Packet-switched on-chip interconnection network for system-on-chip applications [My Copy] Circuits and Systems II: Express Briefs, IEEE Transactions on, Vol. 52, No. 6. (05 July 2005), pp. 308-312. by Se-Joong Lee, Kangmin Lee, Seong-Jun Song, Hoi-Jun Yoo posted to thesis noc interconnect belinda by belin87 on 2009-09-29 15:12:06 as
	On-Chip Interconnection Networks of the TRIPS Chip [My Copy] Micro, IEEE, Vol. 27, No. 5. (12 November 2007), pp. 41-50. by P. Gratz, Changkyu Kim, K. Sankaralingam, et al.H. Hanson, P. Shivakumar, S. W. Keckler, D. Burger posted to thesis noc interconnect belinda by belin87 on 2009-09-29 15:10:32 as
	Combating digital noise in high speed ULSI circuits using binary BCH encoding [My Copy] Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on, Vol. 4 (06 August 2002), pp. 13-16 vol.4. by D. Pamunuwa, Li-Rong Zheng, Hannu Tenhunen posted to interconnect error-correction by mrsmond on 2009-09-23 12:14:08 as
	Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks [My Copy] High-Performance Computer Architecture, International Symposium on In High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on, Vol. 0 (2003), pp. 91-102. by Li Shang, Li S. Peh, Niraj K. Jha posted to interconnect energy-analysis dynamic-voltage-scaling by mrsmond on 2009-09-10 12:09:26 as along with 1 person dtsamis
	Toward achieving energy efficiency in presence of deep submicron noise [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on In Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 8, No. 4. (2000), pp. 379-391. by R. Hegde, N. R. Shanbhag posted to energy-analysis error-correction fault-tolerance interconnect by mrsmond on 2009-07-24 16:01:27 as
	A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip [My Copy] In CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis (2003), pp. 188-193. by Heiko Zimmer, Axel Jantsch posted to fault-tolerance interconnect network-on-chip reliability by mrsmond on 2009-07-24 15:52:46 as
	Quality-of-service and error control techniques for mesh-based network-on-chip architectures [My Copy] Integration, the VLSI Journal, Vol. 38, No. 3. (January 2005), pp. 353-382. by P. Vellanki, N. Banerjee, K. Chatha posted to fault-tolerance interconnect reliability transient-faults by mrsmond on 2009-07-24 15:50:56 as
	Coding for system-on-chip networks: a unified framework [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on In Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 13, No. 6. (2005), pp. 655-667. by S. R. Sridhara, N. R. Shanbhag posted to interconnect reliability by mrsmond on 2009-07-24 15:45:19 as
	Characteristic Impedance Model for Plasmonic Metal Slot Waveguides [My Copy] Selected Topics in Quantum Electronics, IEEE Journal of In Selected Topics in Quantum Electronics, IEEE Journal of, Vol. 14, No. 6. (2008), pp. 1473-1478. by D. S. Ly Gagnon, S. E. Kocaba¿, D. A. B. Miller posted to interconnect metal optical photodiode waveguide by dalyx on 2009-01-12 20:40:15 as
	Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications [My Copy] Electron Devices, IEEE Transactions on In Electron Devices, IEEE Transactions on, Vol. 54, No. 12. (2007), pp. 3206-3215. by Kyung H. Koo, Hoyeol Cho, P. Kapur, K. C. Saraswat posted to interconnect by dalyx on 2008-12-15 23:54:53 as
	The Delay, Energy, and Bandwidth Comparisons between Copper, Carbon Nanotube, and Optical Interconnects for Local and Global Wiring Application [My Copy] International Interconnect Technology Conference, IEEE 2007 In International Interconnect Technology Conference, IEEE 2007 (2007), pp. 135-137. by Hoyeol Cho, Kyung H. Koo, P. Kapur, K. C. Saraswat posted to interconnect by dalyx on 2008-12-15 23:54:25 as
	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on In Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 9, No. 6. (2001), pp. 899-912. by R. Venkatesan, J. A. Davis, K. A. Bowman, J. D. Meindl posted to interconnect optimization by sbadel on 2008-10-28 16:00:04 as
	New formulas of interconnect capacitances based on results of conformal mapping method [My Copy] Electron Devices, IEEE Transactions on In Electron Devices, IEEE Transactions on, Vol. 47, No. 1. (2000), pp. 222-231. by F. Stellari, A. L. Lacaita posted to capacitance fringe interconnect by sbadel on 2008-10-28 15:55:06 as
	Neck development in metal/elastomer bilayers under dynamic stretchings [My Copy] International Journal of Solids and Structures In Special Issue Honoring K.C. Hwang - Fracture, Plasticity, Micro- and Nanomechanics, Special Issue Honoring K.C. Hwang, Vol. 45, No. 13. (30 June 2008), pp. 3769-3778. by Zhenyu Xue, John W. Hutchinson posted to 2008 ductility hutchinson ijss interconnect localization mechanics modeling necking polymer-substrate stretchability thin-metal-film by Macroelectronics to the group Macroelectronics on 2008-06-30 19:35:09 as along with 1 person ZhaoZhang
	Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 [My Copy] Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on In Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on (2007), pp. 3-14. by Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi posted to cache cacti interconnect non-uniform-cache simulator by mamadoudiao on 2008-05-13 16:50:07 as
	A NUCA model for embedded systems cache design [My Copy] Embedded Systems for Real-Time Multimedia, 2005. 3rd Workshop on In Embedded Systems for Real-Time Multimedia, 2005. 3rd Workshop on (2005), pp. 41-46. by P. Foglia, D. Mangano, C. A. Prete posted to cache embedded-processor interconnect memory-access-pattern non-uniform-cache by mamadoudiao on 2008-05-13 16:43:45 as
	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches [My Copy] In ASPLOS-X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems (2002), pp. 211-222. by Changkyu Kim, Doug Burger, Stephen W. Keckler posted to cache interconnect memory-access-pattern non-uniform-cache by mamadoudiao on 2008-05-02 19:00:01 as along with 1 person dschuff
	Interconnect design considerations for large NUCA caches [My Copy] In ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture (2007), pp. 369-380. by Naveen Muralimanohar, Rajeev Balasubramonian posted to cache interconnect memory-access-pattern non-uniform-cache by mamadoudiao on 2008-05-02 18:54:12 as along with 1 person Fantozzi
	Quantum-dot Field Programmable Gate Array: enhanced routing [My Copy] Optoelectronic and Microelectronic Materials and Devices, 2006 Conference on In Optoelectronic and Microelectronic Materials and Devices, 2006 Conference on (2006), pp. 121-124. by A. Jazbec, N. Zimic, I. L. Bajec, P. Pecar, M. Mraz posted to interconnect qca-prorammable by Ruchi on 2008-04-01 18:42:35 as along with 1 person Tunger
	ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform [My Copy] In HOTI '06: Proceedings of the 14th IEEE Symposium on High-Performance Interconnects (2006), pp. 45-51. by Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata posted to asplos08 eth hoti interconnect interconnects nec pci pci-e by muli on 2008-03-03 15:50:51 as along with 1 person pkt
	Power consumption estimation in CMOS VLSI chips [My Copy] Solid-State Circuits, IEEE Journal of, Vol. 29, No. 6. (1994), pp. 663-670. by Dake Liu, C. Svensson posted to interconnect low power by alagor on 2006-11-26 19:04:04 as along with 1 person Pepijn
	The Design of a Low Energy FPGA [My Copy] Low Power Electronics and Design, 1999. Proceedings. 1999 International Symposium on In Proceedings. 1999 International Symposium on Low Power Electronics and Design (1999), pp. 188-193. by V. George, Hui Zhang, J. Rabaey posted to architecture for_thesis fpga interconnect lut power power_estimation power_measurement routing xilinx by nathalie on 2006-09-01 01:45:28 as
	Low-power High-level Synthesis for FPGA Architectures [My Copy] Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on In Proceedings of the 2003 International Symposium on Low Power Electronics and Design (2003), pp. 134-139. by Deming Chen, J. Cong, Yiping Fan posted to activity fpga interconnect power power_estimation synthesis by nathalie on 2006-09-01 01:34:03 as
	Power Estimation Techniques for FPGAs [My Copy] IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10. (2004), pp. 1015-1027. by J. H. Anderson, F. N. Najm posted to activity for_thesis fpga interconnect power power_estimation vlsi xilinx by nathalie on 2006-09-01 01:12:59 as along with 1 person ceegrs2
	Directional and single-driver wires in FPGA interconnect [My Copy] Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (2004), pp. 41-48. by G. Lemieux, E. Lee, M. Tom, A. Yu posted to altera architecture for_thesis fpga interconnect routing xilinx by nathalie on 2006-08-28 04:10:16 as
	A New Switch Block for Segmented FPGAs [My Copy] In FPL '99: Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications (1999), pp. 274-281. by Imran M. Masud, Steven J. E. Wilton posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:24:42 as
	Universal switch modules for FPGA design [My Copy] ACM Trans. Des. Autom. Electron. Syst., Vol. 1, No. 1. (January 1996), pp. 80-101. by Yao-Wen Chang, D. F. Wong, C. K. Wong posted to architecture for_thesis fpga interconnect routing by nathalie on 2006-08-11 06:21:38 as
	On two-step routing for FPGAS [My Copy] In ISPD '97: Proceedings of the 1997 international symposium on Physical design (1997), pp. 60-66. by Guy G. F. Lemieux, Stephen D. Brown, Daniel Vranesic posted to architecture for_thesis interconnect routing xilinx by nathalie on 2006-08-11 06:12:00 as
	Stretchable interconnects for elastic electronic surfaces [My Copy] Proceedings of the IEEE, Vol. 93, No. 8. (2005), pp. 1459-1467. by S. P. Lacour, J. Jones, S. Wagner, Teng Li, Zhigang Suo posted to applications flexible-electronics interconnect macroelectronics materials mechanics polymer-substrate stretchability technology by Macroelectronics on 2006-07-03 02:44:04 as along with 2 people and 1 group liteng suopublications Macroelectronics
	Specular spectral profilometry on metal layers [My Copy] Metrology, Inspection, and Process Control for Microlithography XIV, Vol. 3998, No. 1. (2000), pp. 882-892. by Junwei Bao, Xinhui Niu, Nickhil H. Jakatdar, Costas J. Spanos, Joseph J. Bendik edited by Neal T. Sullivan posted to interconnect metrology scatterometry by kewms on 2006-06-02 18:28:48 as
	Circuit design, transistor sizing and wire layout of FPGA interconnect [My Copy] Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 (1999), pp. 171-174. by V. Betz, J. Rose posted to fpga interconnect vlsi by nathalie on 2005-11-04 03:21:52 as along with 1 person gane5h
	A power-optimal repeater insertion methodology for global interconnects in nanometer designs [My Copy] Electron Devices, IEEE Transactions on, Vol. 49, No. 11. (2002), pp. 2001-2007. by K. Banerjee, A. Mehrotra posted to interconnect low power repeater by mobius2004 on 2005-09-15 19:19:21 as
	Low power repeaters driving RC interconnects with delay and bandwidth constraints [My Copy] SOC Conference, 2004. Proceedings. IEEE International (2004), pp. 335-339. by Guoqing Chen, E. G. Friedman posted to bandwidth interconnect low power repeater by mobius2004 on 2005-09-15 19:14:33 as
	A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations [My Copy] In ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design (2005), pp. 131-136. by Vineet Wason, Kaustav Banerjee posted to interconnect process repeater variations by mobius2004 on 2005-09-15 19:11:43 as
	Interconnect Effort - A Unification of Repeater Insertion and Logical Effort [My Copy] In ISVLSI '03: Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03) (2003) by Srividya Srinivasaraghavan, Wayne Burleson posted to effort interconnect logical repeater by mobius2004 on 2005-09-15 19:08:56 as
	Exploiting the on-chip inductance in high-speed clock distribution networks [My Copy] IEEE Trans. Very Large Scale Integr. Syst., Vol. 9, No. 6. (December 2001), pp. 963-973. by Yehea I. Ismail, Eby G. Friedman, Jose L. Neves posted to clock inductance interconnect by mobius2004 on 2005-09-15 19:00:44 as along with 1 person and 2 groups A_Olympia Philosophy_of_Information Blog_and_Wiki_Research
	Repeater insertion in tree structured inductive interconnect [My Copy] In ICCAD '99: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design (1999), pp. 420-424. by Yehea I. Ismail, Eby G. Friedman, Jose L. Neves posted to inductance interconnect repeater by mobius2004 on 2005-09-15 18:59:26 as
	Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects [My Copy] Design Automation Conference, 2001. Proceedings (2001), pp. 798-803. by K. Banerjee, A. Mehrotra posted to inductance interconnect rlc by mobius2004 on 2005-09-15 18:57:30 as
	Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling [My Copy] VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on (2001), pp. 195-198. by K. Banerjee, A. Mehrotra posted to inductance interconnect repeater by mobius2004 on 2005-09-15 18:56:05 as
	Analysis of on-chip inductance effects for distributed RLC interconnects [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 21, No. 8. (2002), pp. 904-915. by K. Banerjee, A. Mehrotra posted to inductance interconnect rlc by mobius2004 on 2005-09-15 18:54:48 as along with 1 person walteryhli
	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 8, No. 2. (2000), pp. 195-206. by Y. I. Ismail, E. G. Friedman posted to delay interconnect repeater by mobius2004 on 2005-09-15 18:38:10 as
	Variational delay metrics for interconnect timing analysis [My Copy] Design Automation Conference, 2004. Proceedings. 41st (2004), pp. 381-384. by K. Agarwal, D. Sylvester, D. Blaauw, F. Liu, S. Nassif, S. Vrudhula posted to interconnect process variation by mobius2004 on 2005-09-15 18:23:14 as
	Process roadmap and challenges for metal barriers [copper interconnects] [My Copy] Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International (2003), pp. 35.1.1-35.1.4. by P. Moon, V. Dubin, S. Johnston, J. Leu, K. Raol, C. Wu posted to copper interconnect by kewms on 2005-09-13 16:01:59 as
	Technology and reliability constrained future copper interconnects. I. Resistance modeling [My Copy] Electron Devices, IEEE Transactions on, Vol. 49, No. 4. (2002), pp. 590-597. by P. Kapur, J. P. Mcvittie, K. C. Saraswat posted to copper interconnect by kewms on 2005-09-13 15:49:41 as
	Cu Planarization for ULSI Processing by Electrochemical Methods: A Review [My Copy] Semiconductor Manufacturing, IEEE Transactions on, Vol. 18, No. 3. (2005), pp. 341-349. by I. I. Suni, B. Du posted to copper interconnect polishing by kewms on 2005-09-13 14:58:32 as
	Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed <italic>RLC</italic> interconnects [My Copy] In DAC '01: Proceedings of the 38th conference on Design automation (2001), pp. 798-803. by Kaustav Banerjee, Amit Mehrotra posted to inductance interconnect by mobius2004 on 2005-09-13 01:25:31 as
	Electronic properties of multiwalled carbon nanotubes in an embedded vertical array [My Copy] Applied Physics Letters, Vol. 81, No. 5. (2002), pp. 910-912. by Jun Li, Ramsey Stevens, Lance Delzeit, et al.Hou T. Ng, Alan Cassell, Jie Han, M. Meyyappan posted to interconnect by cardinal on 2005-08-31 19:15:18 as

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reliability	21
fpga	12
belinda	10
thesis	10
architecture	9
routing	9
repeater	7
for_thesis	6
inductance	6
noc	6
power	6
cache	4
ieee_micro	4
mechanics	4
non-uniform-cache	4
polymer-substrate	4
stretchability	4
xilinx	4
altera	3
copper	3
fault-tolerance	3
flexible-electronics	3
low	3
macroelectronics	3
memory-access-pattern	3
power_estimation	3
2008	2
activity	2
applications	2
ductility	2
energy-analysis	2
error-correction	2
hutchinson	2
ijss	2
localization	2
materials	2
modeling	2
necking	2
printed	2
process	2
rlc	2
technology	2
thin-metal-film	2
vlsi	2
asplos08	1
bandwidth	1
cacti	1
capacitance	1
clock	1
delay	1
dynamic-voltage-scaling	1
effort	1
embedded-processor	1
eth	1
fringe	1
hoti	1
interconnects	1
layout	1
logical	1
lut	1
mask_programmable	1
metal	1
metrology	1
microfludic	1
nec	1
network-on-chip	1
optical	1
optimization	1
pci	1
pci-e	1
photodiode	1
polishing	1
power_measurement	1
qca-prorammable	1
regular_fabric	1
review	1
scatterometry	1
simulator	1
structured_asic	1
switch_block	1
synthesis	1
transient-faults	1
variation	1
variations	1
via_programmable	1
vpga	1
waveguide	1
wavelength_routing	1
wavep	1

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