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	Does the location of aircraft nitrogen oxide emissions affect their climate impact? [My Copy] Geophysical Research Letters, Vol. 36, No. 17. (11 September 2009), L17810. by David S. Stevenson, Richard G. Derwent posted to transport nox multiplier flight emissions aircraft by DanHodson on 2009-11-23 18:26:50 as along with 1 person alupu
	Systematic IEEE rounding method for high-speed floating-point multipliers [My Copy] IEEE Trans. Very Large Scale Integr. Syst., Vol. 12, No. 5. (2004), pp. 511-521. by Nhon T. Quach, Naofumi Takagi, Michael J. Flynn posted to floating-point floating-point-multiplication floating-point-multiplier ieee-754 ieee-rouding multiplier by thang_spsc on 2009-02-04 08:51:59 as
	Rounding algorithms for IEEE multipliers [My Copy] Computer Arithmetic, 1989., Proceedings of 9th Symposium on In Computer Arithmetic, 1989., Proceedings of 9th Symposium on (1989), pp. 176-183. by M. R. Santoro, G. Bewick, M. A. Horowitz posted to algorithm floating-point floating-point-arithmetic ieee-rounding multiplier rouding rounding-algorithm by thang_spsc on 2009-02-02 08:08:27 as along with 1 person periodic
	Low complexity bit parallel architectures for polynomial basis multiplication over GF(2m) [My Copy] Computers, IEEE Transactions on In Computers, IEEE Transactions on, Vol. 53, No. 8. (2004), pp. 945-959. by A. Reyhani-Masoleh, M. A. Hasan posted to galois multiplier by csue on 2009-02-01 19:02:54 as
	A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme [My Copy] Computers, IEEE Transactions on In Computers, IEEE Transactions on, Vol. 56, No. 11. (2007), pp. 1470-1483. by N. Petra, D. De Caro, A. G. M. Strollo posted to galois multiplier by csue on 2009-02-01 18:47:15 as along with 1 person peskin
	Reconstruction of Nonuniformly Sampled Bandlimited Signals Using a Differentiator-Multiplier Cascade [My Copy] Circuits and Systems I: Regular Papers, IEEE Transactions on In IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 55, No. 8. (September 2008), pp. 2273-2286. by Stefan Tertinek, Christian Vogel posted to analog-to- analog-to-digital converter differentiator digital discrete-time expansion farrow multiplier nonuniform sampling series structure taylor ti-adc time-interleaved time-varying by peteru on 2008-09-22 09:36:57 as
	The "quiet" state-a new approach to low-power multiplier design [My Copy] Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, Vol. 2 (2003), pp. 2222-2226 Vol.2. by N. Mallios, N. Burgess posted to activity arithmetic for_thesis multiplier power by nathalie on 2006-10-02 05:07:12 as
	Wormhole run-time reconfiguration [My Copy] In FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays (1997), pp. 79-85. by Ray Bittner, Peter Athanas posted to architecture floating_point fpga multiplier printed reconfigurable_computing runtime_reconfig by nathalie on 2006-04-30 23:42:42 as
	Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation [My Copy] In GLS '99: Proceedings of the Ninth Great Lakes Symposium on VLSI (1999) by Janardhan H. Satyanarayana, Keshab K. Parhi posted to arithmetic dsp for_thesis multiplier power power_estimation by nathalie on 2006-04-18 16:58:07 as
	Architectural power analysis: The dual bit type method [My Copy] Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Vol. 3, No. 2. (1995), pp. 173-187. by P. E. Landman, J. M. Rabaey posted to adder architecture arithmetic for_thesis fpl_paper multiplier power power_estimation printed by nathalie on 2006-03-05 02:24:58 as along with 1 person ceegrs2
	Synthesis of low power linear DSP circuits using activity metrics [My Copy] VLSI Design, 1994., Proceedings of the Seventh International Conference on (1994), pp. 265-270. by A. Chatterjee, R. K. Roy posted to adder arithmetic dsp multiplier power power_estimation printed synthesis by nathalie on 2006-03-05 01:39:45 as
	A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure [My Copy] FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on (1998), pp. 226-234. by S. D. Haynes, P. Y. K. Cheung posted to altera architecture arithmetic embedded for_thesis fpga fpl_paper image_processing multiplier printed xilinx by nathalie on 2006-01-10 23:48:14 as
	Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs [My Copy] Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 (1999), pp. 191-194. by S. D. Haynes, A. B. Ferrari, P. Y. K. Cheung posted to altera architecture arithmetic for_thesis fpga fpl_paper multiplier printed xilinx by nathalie on 2005-06-22 06:32:37 as
	A flexible multiplication unit for an FPGA logic block [My Copy] Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Vol. 4 (2001), pp. 546-549 vol. 4. by K. Rajagopalan, P. Sutton posted to arithmetic fpga multiplier xilinx by nathalie on 2005-06-22 06:18:49 as
	An Arithmetic Library and Its Application to the N-body Problem [My Copy] In FCCM '04: Proceedings of the Field-Programmable Custom Computing Machines, 12th Annual IEEE Symposium on (FCCM'04) (2004), pp. 68-78. by K. H. Tsoi, C. H. Ho, H. C. Yeung, P. H. W. Leong posted to adder arithmetic fpga multiplier xilinx by nathalie on 2005-06-15 21:58:17 as
	A fast-multiplier generator for FPGAs [My Copy] VLSI Design, 1995., Proceedings of the 8th International Conference on (1995), pp. 53-56. by S. Kumar, K. Forward, M. Palaniswami posted to arithmetic fpga multiplier xilinx by nathalie on 2005-06-15 08:25:07 as
	Reduced power dissipation through truncated multiplication [My Copy] Low-Power Design, 1999. Proceedings. IEEE Alessandro Volta Memorial Workshop on (1999), pp. 61-69. by M. Schulte, J. Stine, J. Jansen posted to arithmetic multiplier power by nathalie on 2005-06-09 00:46:51 as
	Exploring multiplier architecture and layout for low power [My Copy] Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996 (1996), pp. 513-516. by P. Meier, R. Rutenbar, L. Carley posted to architecture arithmetic multiplier power by nathalie on 2005-06-08 22:21:43 as
	Low-power high-performance arithmetic circuits and architectures [My Copy] Solid-State Circuits, IEEE Journal of, Vol. 37, No. 1. (2002), pp. 90-94. by A. Fahim, M. Elmasry posted to adder architecture arithmetic coarse_grained_architectures multiplier power by nathalie on 2005-06-08 19:57:41 as
	Low power parallel multipliers [My Copy] VLSI Signal Processing, IX, 1996., [Workshop on] (1996), pp. 199-208. by E. de Angel, E. Swartzlander posted to arithmetic multiplier power printed vlsi by nathalie on 2005-05-16 22:21:23 as

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