Gate leakage reduction for scaled devices using transistor stacking Export

@article{citeulike:6066108, abstract = {In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L_eff) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44\% savings in total leakage in 50-nm devices compared to the conventional stacking technique.}, author = {Mukhopadhyay, S. and Neau, C. and Cakici, R. T. and Agarwal, A. and Kim, C. H. and Roy, K.}, citeulike-article-id = {6066108}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TVLSI.2003.816145}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1229877}, day = {08}, doi = {10.1109/TVLSI.2003.816145}, journal = {Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, keywords = {leakagecurrent}, month = {September}, number = {4}, pages = {716--730}, posted-at = {2009-11-04 01:17:32}, priority = {2}, title = {Gate leakage reduction for scaled devices using transistor stacking}, url = {http://dx.doi.org/10.1109/TVLSI.2003.816145}, volume = {11}, year = {2003} }

TY - JOUR ID - citeulike:6066108 L3 - citeulike-article-id:6066108 N2 - In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L_eff) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique. IS - 4 JF - Very Large Scale Integration (VLSI) Systems, IEEE Transactions on EP - 730 TI - Gate leakage reduction for scaled devices using transistor stacking VL - 11 SP - 716 KW - leakagecurrent AU - Mukhopadhyay, S AU - Neau, C AU - Cakici, RT AU - Agarwal, A AU - Kim, CH AU - Roy, K PY - 2003/09/08/ UR - http://dx.doi.org/10.1109/TVLSI.2003.816145 ER -