NickGasson's synthesis [32 articles] Export

Recent papers added to NickGasson's library classified by the tag synthesis. You can also see everyone's synthesis.

	Force-directed scheduling in automatic data path synthesis [My Copy] In DAC '87: Proceedings of the 24th ACM/IEEE conference on Design automation (1987), pp. 195-202. by P. G. Paulin, J. P. Knight posted to scheduling synthesis by NickGasson on 2009-05-04 17:39:44 as
	The MIMOLA design system: Tools for the design of digital processors [My Copy] In DAC '84: Proceedings of the 21st conference on Design automation (1984), pp. 587-593. by Peter Marwedel posted to synthesis by NickGasson on 2009-05-04 14:19:39 as
	Macro-based hardware compilation of java bytecodes into a dynamic reconfigurable computing system [My Copy] In IEEE Symposium on FieldProgrammable Custom Computing Machines (1999), pp. 2-11. by João M. P. Cardoso posted to java synthesis by NickGasson on 2009-01-15 13:29:15 as
	High-level Synthesis for Highly Concurrent Hardware Systems [My Copy] Application of Concurrency to System Design, International Conference on, Vol. 0 (2006), pp. 79-90. by Sunan Tugsinavisut, Roger Su, Peter A. Beerel posted to synthesis by NickGasson on 2008-12-09 19:07:22 as
	A formal approach to the scheduling problem in high level synthesis [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 10, No. 4. (1991), pp. 464-475. by C. T. Hwang, J. H. Lee, Y. C. Hsu posted to scheduling synthesis by NickGasson on 2008-11-24 10:55:30 as
	Synthesis and Optimization of Digital Circuits [My Copy] (1994) by Giovanni De Micheli posted to digital-logic synthesis by NickGasson on 2008-11-24 10:08:37 as
	Bidwidth analysis with application to silicon compilation [My Copy] SIGPLAN Not., Vol. 35, No. 5. (2000), pp. 108-120. by Mark Stephenson, Jonathan Babb, Saman Amarasinghe posted to compilers synthesis by NickGasson on 2008-11-24 10:04:43 as
	Bitwidth-aware scheduling and binding in high-level synthesis [My Copy] In ASP-DAC '05: Proceedings of the 2005 conference on Asia South Pacific design automation (2005), pp. 856-861. by Jason Cong, Yiping Fan, Guoling Han, et al.Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng posted to synthesis by NickGasson on 2008-11-14 15:16:06 as
	SALSA: A New Approach to Scheduling with Timing Constraints [My Copy] (1993) by John A. Nestor, Senior Member, Ganesh Krishnamoorthy posted to scheduling synthesis by NickGasson on 2008-11-14 15:04:59 as
	MAHA: a program for datapath synthesis [My Copy] In DAC '86: Proceedings of the 23rd ACM/IEEE conference on Design automation (1986), pp. 461-466. by Alice C. Parker, Jorge T. Pizarro, Mitch Mlinar posted to synthesis by NickGasson on 2008-11-14 15:03:13 as
	Algorithms for hardware allocation in data path synthesis [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 8, No. 7. (1989), pp. 768-781. by S. Devadas, A. R. Newton posted to synthesis by NickGasson on 2008-11-14 15:01:58 as
	Speculation techniques for high level synthesis of control intensive designs [My Copy] In DAC '01: Proceedings of the 38th conference on Design automation (2001), pp. 269-272. by Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil Dutt, Rajesh Gupta, Alex Nicolau posted to synthesis by NickGasson on 2008-11-13 16:07:53 as
	Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions [My Copy] In DAC '98: Proceedings of the 35th annual conference on Design automation (1998), pp. 108-113. by Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha posted to compilers synthesis by NickGasson on 2008-11-13 16:07:01 as
	Conditional Speculation and Its Effects on Performance and Area for High-Level Synthesis [My Copy] System Synthesis, International Symposium on, Vol. 0 (2001), pp. 171-176. by Alex Nicolau, Nikil Dutt, Rajesh Gupta, Nick Savoiu, Sumit Gupta posted to synthesis by NickGasson on 2008-11-13 16:06:09 as
	A genetic algorithm for the design space exploration of datapaths during high-level synthesis [My Copy] Evolutionary Computation, IEEE Transactions on In Evolutionary Computation, IEEE Transactions on, Vol. 10, No. 3. (2006), pp. 213-229. by V. Krishnan, S. Katkoori posted to nsc synthesis by NickGasson on 2008-11-13 13:57:56 as
	SPARK: A High-Level Synthesis Framework For Applying Parallelizing Compiler Transformations [My Copy] VLSI Design, International Conference on, Vol. 0 (2003) by Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alex Nicolau posted to compilers synthesis by NickGasson on 2008-11-13 13:56:45 as
	Fast prototyping of datapath-intensive architectures [My Copy] Design & Test of Computers, IEEE In Design & Test of Computers, IEEE, Vol. 8, No. 2. (1991), pp. 40-51. by J. M. Rabaey, C. Chu, P. Hoang, M. Potkonjak posted to synthesis by NickGasson on 2008-11-03 14:22:42 as
	High level synthesis for reconfigurable datapath structures [My Copy] In ICCAD '93: Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design (1993), pp. 26-29. by Lisa Guerra, Miodrag Potkonjak, Jan Rabaey posted to synthesis by NickGasson on 2008-11-03 13:43:35 as
	Behavioral Model Synthesis with Cones [My Copy] IEEE Design and Test of Computers, Vol. 5, No. 3. (1988), pp. 22-30. by Charles E. Stroud, Ronald R. Munoz, David A. Pierce posted to synthesis by NickGasson on 2008-10-16 15:57:03 as
	Flamel: A High-Level Hardware Compiler [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 6, No. 2. (1987), pp. 259-269. by H. Trickey posted to hw-compilation synthesis by NickGasson on 2008-10-16 10:56:25 as
	Representation of control and timing behavior with applications to interface synthesis [My Copy] Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on In Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on (1988), pp. 382-387. by S. A. Hayati, A. C. Parker, J. J. Granacki posted to synthesis by NickGasson on 2008-10-16 10:55:49 as
	Architectural synthesis for DSP silicon compilers [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 8, No. 4. (1989), pp. 431-447. by B. Haroun, M. I. Elmasry posted to synthesis by NickGasson on 2008-10-15 17:44:46 as
	Synthesis of hardware models in C with pointers and complex data structures [My Copy] IEEE Transactions on VLSI Systems, Vol. 9 (2001), pp. 743-756. by Luc Séméria, Koichi Sato, Giovanni De Micheli posted to hw-compilation synthesis by NickGasson on 2008-10-15 17:43:37 as
	Hardware Synthesis from C/C++ Models [My Copy] In Proc. Design, Automation and Test in Europe Conference and Exhibition, Vol. 99 (1999), pp. 382-383. by Giovanni De Micheli posted to synthesis by NickGasson on 2008-10-15 17:42:00 as
	High level synthesis of ASICs under timing and synchronization constraints [My Copy] (1992) by David C. Ku, Giovanni De Micheli posted to synthesis by NickGasson on 2008-10-15 17:40:26 as
	Introduction to high-level synthesis [My Copy] Design & Test of Computers, IEEE In Design & Test of Computers, IEEE, Vol. 11, No. 4. (06 August 2002), pp. 44-54. by D. D. Gajski, L. Ramachandran posted to synthesis by NickGasson on 2008-10-09 14:28:42 as along with 1 person skolaric
	The high-level synthesis of digital systems [My Copy] Proceedings of the IEEE In Proceedings of the IEEE, Vol. 78, No. 2. (1990), pp. 301-318. by M. C. Mcfarland, A. C. Parker, R. Camposano posted to synthesis by NickGasson on 2008-10-09 14:27:33 as
	Soft Scheduling in High Level Synthesis [My Copy] Design Automation Conference, Vol. 0 (1999), pp. 219-224. by Jianwen Zhu, Daniel D. Gajski posted to synthesis by NickGasson on 2008-10-07 11:44:10 as
	Path-based scheduling for synthesis [My Copy] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 10, No. 1. (1991), pp. 85-93. by R. Camposano posted to synthesis by NickGasson on 2008-10-07 11:40:41 as
	Latch Based Interconnect Pipelining For High Speed Integrated Circuits [My Copy] Electro/information Technology, 2006 IEEE International Conference on In Electro/information Technology, 2006 IEEE International Conference on (2006), pp. 295-300. by Jingye Xu, M. H. Chowdhury posted to digital-logic synthesis by NickGasson on 2008-10-06 10:54:06 as
	Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis [My Copy] High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International In High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International (2006), pp. 162-169. by Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita posted to synthesis by NickGasson on 2008-10-06 10:45:23 as
	Algorithms for High-Level Synthesis [My Copy] IEEE Des. Test, Vol. 6, No. 6. (1989), pp. 18-31. by Pierre G. Paulin, John P. Knight posted to compilers synthesis by NickGasson on 2008-10-06 10:23:48 as

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synthesis	32
compilers	28
hw-compilation	21
fpgas	20
comp-arch	14
hll-arch	12
scheduling	12
hdls	9
codesign	8
sw-arch	7
sw-lang	7
digital-logic	5
haskell	5
reconfiguration	5
vliw	5
hw-arch	4
compression	3
cryptography	3
java	3
nisc	3
nsc	3
predictable	3
asip	2
coordination	2
electronics	2
fsms	2
jit	2
lisp	2
mapping	2
semantics	2
sw-eng	2
algorithms	1
evaluation	1
fpga	1
handel-c	1
local-search	1
manual	1
maths	1
mine	1
music	1
operating-systems	1
parsing	1
power	1
pr	1
rts	1

NickGasson's synthesis [32 articles] Export

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