VLSI architectures for soft-decision decoding of Reed-Solomon codes Export

@proceedings{AhmedKoetter_VLSISoftDecision_2003, abstract = {We present the architectures for bivariate polynomial interpolation and factorization; the two main steps in algebraic soft-decision decoding of Reed-Solomon codes. We present an efficient formulation of the interpolation algorithm in which dependencies among the discrepancy coefficient computations are utilized to reduce interpolation complexity. Interpolation and factorization complexity is also reduced by using an FFT-like formulation for univariate polynomial translation. The modifications required to incorporate the recently proposed algorithm level modifications for efficient interpolation and factorization are also presented. We determine the latency and hardware requirements for soft-decoding a [255,239] Reed-Solomon code using the proposed architectures.}, author = {Ahmed, A. and Koetter, R. and Shanbhag, N. R.}, citeulike-article-id = {493467}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ICC.2004.1312999}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1312999}, day = {26}, doi = {10.1109/ICC.2004.1312999}, journal = {Communications, 2004 IEEE International Conference on}, keywords = {coding, list, soft\_decision}, month = {July}, pages = {2584--2590 Vol.5}, posted-at = {2009-10-20 07:58:43}, priority = {2}, title = {VLSI architectures for soft-decision decoding of Reed-Solomon codes}, url = {http://dx.doi.org/10.1109/ICC.2004.1312999}, volume = {5}, year = {2004} }

TY - CONF ID - AhmedKoetter_VLSISoftDecision_2003 L3 - citeulike-article-id:493467 N2 - We present the architectures for bivariate polynomial interpolation and factorization; the two main steps in algebraic soft-decision decoding of Reed-Solomon codes. We present an efficient formulation of the interpolation algorithm in which dependencies among the discrepancy coefficient computations are utilized to reduce interpolation complexity. Interpolation and factorization complexity is also reduced by using an FFT-like formulation for univariate polynomial translation. The modifications required to incorporate the recently proposed algorithm level modifications for efficient interpolation and factorization are also presented. We determine the latency and hardware requirements for soft-decoding a [255,239] Reed-Solomon code using the proposed architectures. JF - Communications, 2004 IEEE International Conference on EP - 2590 Vol.5 TI - VLSI architectures for soft-decision decoding of Reed-Solomon codes VL - 5 SP - 2584 KW - coding KW - list KW - soft_decision AU - Ahmed, A AU - Koetter, R AU - Shanbhag, NR PY - 2004/07/26/ UR - http://dx.doi.org/10.1109/ICC.2004.1312999 ER -