The FLaSH Compiler: Efficient Circuits from Functional Specifications
In previous work we have outlined the design of a functional language, SAFL, and argued that it is well suited to hardware description and synthesis. Unlike conventional high-level synthesis languages, SAFL specifications capture explicitly resource allocation, variable binding and scheduling. This paper is concerned with the details of the FLaSH compiler: an optimising silicon compiler which translates SAFL specifications to RTL Verilog suitable for simulation or synthesis. We describe a number of high-level optimisation and analysis techniques which find novel application in the field of hardware-synthesis. In particular, we believe our approach to compiling function de nitions into shared resources could be applied advantageously in existing industrial silicon compilers.