Global instruction scheduling in dynamic compilation for embedded systems

The application fields of bytecode virtual machines and Very Long Instruction Word (VLIW) processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to instruction scheduling, which is required in VLIW architectures. While the rewards for dynamic optimization may be high, the trade-offs between optimization benefits and overheads must be fully understood.To this end, we have extended the work of the original JIST project [1], a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor, to include a full implementation of a superblock scheduler. We show the impact of global scheduling on the performance of code compiled with JIST through the experimental study of a set of benchmark programs. We report significant speedups with respect to the local scheduling version of the JIST compiler.