Performance analysis and optimisation of NCL self-timed rings Export

@article{j_kuang_yuan_ipcds_03, abstract = {A self-timed ring using NULL convention logic (NCL) is presented. An analytical method to evaluate the speed of NCL rings has been developed. The analytical predictions are verified by a Synopsys simulation and excellent agreement between the theoretical predictions and simulation results is obtained. Some important principles for ring optimisation are obtained. The analysis leads to the speed optimisation of a 24-bit NCL divider.}, author = {Kuang, W. and Yuan, J. and Demara, R. and Hagedorn, M. and Fant, K.}, citeulike-article-id = {121660}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1214760}, journal = {Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems]}, keywords = {demara}, number = {3}, pages = {167--172}, posted-at = {2005-03-11 15:10:47}, priority = {2}, title = {Performance analysis and optimisation of NCL self-timed rings}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1214760}, volume = {150}, year = {2003} }

TY - JOUR ID - j_kuang_yuan_ipcds_03 L3 - citeulike-article-id:121660 N2 - A self-timed ring using NULL convention logic (NCL) is presented. An analytical method to evaluate the speed of NCL rings has been developed. The analytical predictions are verified by a Synopsys simulation and excellent agreement between the theoretical predictions and simulation results is obtained. Some important principles for ring optimisation are obtained. The analysis leads to the speed optimisation of a 24-bit NCL divider. IS - 3 JF - Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems] EP - 172 TI - Performance analysis and optimisation of NCL self-timed rings VL - 150 SP - 167 KW - demara AU - Kuang, W AU - Yuan, J AU - Demara, R AU - Hagedorn, M AU - Fant, K PY - 2003/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1214760 ER -