Delay-insensitive gate-level pipelining Export

@article{j_smith_demara_ivlsi_01, abstract = {Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit x 4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.}, author = {Smith, S. and Demara, R. and Yuan, J. and Hagedorn, M. and Ferguson, D.}, citeulike-article-id = {87078}, citeulike-linkout-0 = {http://dx.doi.org/10.1016/S0167-9260(01)00013-X}, citeulike-linkout-1 = {http://www.sciencedirect.com/science/article/B6V1M-449TT5X-1/2/2a7d16e3a721cc28b8b41012b9425f13}, doi = {10.1016/S0167-9260(01)00013-X}, journal = {Integration, the VLSI Journal}, keywords = {demara}, month = {October}, number = {2}, pages = {103--131}, posted-at = {2005-02-03 17:39:52}, priority = {2}, title = {Delay-insensitive gate-level pipelining}, url = {http://dx.doi.org/10.1016/S0167-9260(01)00013-X}, volume = {30}, year = {2001} }

TY - JOUR ID - j_smith_demara_ivlsi_01 L3 - citeulike-article-id:87078 N2 - Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit x 4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity. IS - 2 JF - Integration, the VLSI Journal EP - 131 TI - Delay-insensitive gate-level pipelining VL - 30 SP - 103 KW - demara AU - Smith, S AU - Demara, R AU - Yuan, J AU - Hagedorn, M AU - Ferguson, D PY - 2001/10// UR - http://dx.doi.org/10.1016/S0167-9260(01)00013-X ER -