High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders Export

@inproceedings{c_di_yuan_isvlsi_03, abstract = {In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as with the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-dimensional pipeline gating technique is used to make the designed FIR power aware of the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions.}, address = {Tampa, Florida, U.S.A.}, author = {Di, Jia and Yuan, J. and Demara, R.}, citeulike-article-id = {87081}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1183490}, journal = {VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on}, keywords = {demara}, pages = {260--261}, posted-at = {2005-02-03 17:41:30}, priority = {2}, title = {High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1183490}, year = {2003} }

TY - CONF ID - c_di_yuan_isvlsi_03 L3 - citeulike-article-id:87081 N2 - In regular FIR structure, by pipelining the multipliers one can improve the throughput. But as with the growth of operand word length, the delay in addition process becomes another important constraint. In this paper, a novel fine-grain pipelining scheme for high throughput FIR is proposed. By pipelining multipliers and adders, very high throughput can be achieved. 2-dimensional pipeline gating technique is used to make the designed FIR power aware of the precision of the operands. The average power dissipation and latency are both significantly reduced with changing of input precisions. JF - VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on AD - Tampa, Florida, U.S.A. EP - 261 TI - High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders SP - 260 KW - demara AU - Di, Jia AU - Yuan, J AU - Demara, R PY - 2003/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1183490 ER -