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Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction

Proceedings of the 2001 International Workshop on Logic and Synthesis (12 - 15 June 2001), pp. 185-189.

by S. C. Smith, R. F. Demara, J. S. Yuan, M. Hagedorn, D. Ferguson

posted to demara by carthik on 2005-03-11 18:39:22 as

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