carthik's Yuan:J [9 articles] Export

Recent papers posted to carthik's library by the author Yuan:J. You can also see everyone's Yuan:J.

	Glitch Power Reduction for Low Power IC Design [My Copy] Proceedings of the Ninth Annual NASA Symposium on VLSI Design (8 - 9 November 2000), pp. 7.5.1-7.5.7. by N. Weng, J. S. Yuan, R. F. Demara, D. Ferguson, M. Hagedorn posted to demara by carthik on 2005-03-11 19:03:49 as
	A Delay-insensitive FIR Filter for DSP Applications [My Copy] Proceedings of the Ninth Annual NASA Symposium on VLSI Design (8 - 9 November 2000), pp. 2.2.1-2.2.7. by W. Kuang, J. S. Yuan, R. F. Demara, D. Ferguson, M. Hagedorn posted to demara by carthik on 2005-03-11 19:02:02 as
	Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction [My Copy] Proceedings of the 2001 International Workshop on Logic and Synthesis (12 - 15 June 2001), pp. 185-189. by S. C. Smith, R. F. Demara, J. S. Yuan, M. Hagedorn, D. Ferguson posted to demara by carthik on 2005-03-11 18:39:22 as
	Performance analysis and optimisation of NCL self-timed rings [My Copy] Circuits, Devices and Systems, IEE Proceedings [see also IEE Proceedings G- Circuits, Devices and Systems], Vol. 150, No. 3. (2003), pp. 167-172. by W. Kuang, J. Yuan, R. Demara, M. Hagedorn, K. Fant posted to demara by carthik on 2005-03-11 15:10:47 as
	High throughput power-aware FIR filter design based on fine-grain pipelining multipliers and adders [My Copy] VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on (2003), pp. 260-261. by Jia Di, J. Yuan, R. Demara posted to demara by carthik on 2005-02-03 17:41:30 as
	Delay-insensitive gate-level pipelining [My Copy] Integration, the VLSI Journal, Vol. 30, No. 2. (October 2001), pp. 103-131. by S. Smith, R. Demara, J. Yuan, M. Hagedorn, D. Ferguson posted to demara by carthik on 2005-02-03 17:39:52 as
	NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation [My Copy] Journal of Systems Architecture, Vol. 47, No. 12. (June 2002), pp. 977-998. by S. Smith, R. Demara, J. Yuan, M. Hagedorn, D. Ferguson posted to demara by carthik on 2005-02-03 17:39:29 as
	Optimization of NULL convention self-timed circuits [My Copy] Integration, the VLSI Journal, Vol. 37, No. 3. (August 2004), pp. 135-165. by S. Smith, R. Demara, J. Yuan, D. Ferguson, D. Lamb posted to demara by carthik on 2005-02-03 17:36:52 as
	Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design [My Copy] Integration, the VLSI Journal, Vol. In Press, Corrected Proof by Jia Di, J. Yuan, R. Demara posted to demara by carthik on 2005-02-03 17:34:34 as

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