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	Self-Tuned Congestion Control for Multiprocessor Networks [My Copy] (2000) by M. Thottethodi, Shrewsbury Ma, Mithuna Thottethodi, et al.Mithuna Thottethodi, Alvin R. Lebeck, Alvin R. Lebeck, Shubhendu S. Mukherjee, Shubhendu S. Mukherjee posted to no-tag by cfallin on 2009-09-04 19:46:02 as
	Effect of a finite reassembly buffer on the performance of deflection routing [My Copy] Communications, 1991. ICC '91, Conference Record. IEEE International Conference on In Communications, 1991. ICC '91, Conference Record. IEEE International Conference on (1991), pp. 1637-1646 vol.3. by A. K. Choudhury, N. F. Maxemchuk posted to no-tag by cfallin on 2009-09-02 20:37:36 as
	Flattened Butterfly Topology for On-Chip Networks [My Copy] Microarchitecture, IEEE/ACM International Symposium on In MICRO '07: Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture, Vol. 0 (2007), pp. 172-182. by John Kim, James Balfour, William Dally posted to no-tag by cfallin on 2009-08-28 19:41:58 as along with 1 person visit0r
	Symbiotic Jobscheduling for a Simultaneous Multithreading Processor [My Copy] (2000) by Allan Snavely, Dean M. Tullsen, Multithreading Processor posted to no-tag by cfallin on 2009-08-28 03:21:39 as
	System-Level Performance Metrics for Multiprogram Workloads [My Copy] IEEE Micro In Micro, IEEE, Vol. 28, No. 3. (2008), pp. 42-53. by Stijn Eyerman, Lieven Eeckhout posted to no-tag by cfallin on 2009-08-28 03:17:58 as along with 1 person naoya
	Bounds on Maximum Delay in Networks with Deflection Routing [My Copy] IEEE Transactions on Parallel and Distributed Systems, Vol. 6, No. 7. (1995), pp. 724-732. by Jack T. Brassil, Rene L. Cruz posted to no-tag by cfallin on 2009-08-18 22:02:20 as
	Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture [My Copy] In PACT '04: Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (2004), pp. 111-122. by Seongbeom Kim, Dhruba Chandra, Yan Solihin posted to no-tag by cfallin on 2009-08-16 02:04:23 as along with 1 person Fantozzi
	ROMM routing on mesh and torus networks [My Copy] In SPAA '95: Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures (1995), pp. 275-287. by Ted Nesson, S. Lennart Johnsson posted to no-tag by cfallin on 2009-08-14 20:45:22 as along with 1 person imr1
	Adaptive deadlock- and livelock-free routing with all minimal paths in Torus networks [My Copy] In SPAA '92: Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures (1992), pp. 3-12. by Pablo E. Berman, Luis Gravano, Gustavo D. Pifarré, Jorge L. C. Sanz posted to no-tag by cfallin on 2009-08-14 20:26:45 as
	Stride Scheduling: Deterministic Proportional-Share Resource Management [My Copy] (1995) by Carl A. Waldspurger, William E. Weihl posted to no-tag by cfallin on 2009-07-06 07:54:08 as
	The Power of Priority: NoC Based Distributed Cache Coherency [My Copy] Networks-on-Chip, 2007. NOCS 2007. First International Symposium on In Networks-on-Chip, 2007. NOCS 2007. First International Symposium on (2007), pp. 117-126. by E. Bolotin, Z. Guz, I. Cidon, R. Ginosar, A. Kolodny posted to no-tag by cfallin on 2009-06-07 23:17:49 as
	Fair Queuing Memory Systems [My Copy] In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (2006), pp. 208-222. by Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, James E. Smith posted to micro2006 by cfallin on 2009-06-07 03:29:07 as along with 1 person weirdbluelights
	The torus routing chip [My Copy] Distributed Computing, Vol. 1, No. 4. (1 December 1986), pp. 187-196. by William J. Dally, Charles L. Seitz posted to no-tag by cfallin on 2009-06-03 06:38:33 as
	Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers [My Copy] Micro, IEEE In Micro, IEEE, Vol. 29, No. 1. (2009), pp. 22-32. by O. Mutlu, T. Moscibroda posted to no-tag by cfallin on 2009-05-31 03:56:54 as
	Express Cube Topologies for on-Chip Interconnects [My Copy] High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on In High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on (2009), pp. 163-174. by B. Grot, J. Hestness, S. W. Keckler, O. Mutlu posted to hpca2009 by cfallin on 2009-05-31 03:53:26 as
	Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors [My Copy] In In HPCA-9 (2003), pp. 129-140. by Onur Mutlu, Jared Stark, Chris Wilkerson, Yale Patt posted to hpca2003 by cfallin on 2009-05-31 03:51:54 as
	Flexible Hardware Acceleration for Instruction-Grain Program Monitoring [My Copy] SIGARCH Comput. Archit. News, Vol. 36, No. 3. (2008), pp. 377-388. by Shimin Chen, Michael Kozuch, Theodoros Strigkos, et al.Babak Falsafi, Phillip B. Gibbons, Todd C. Mowry, Vijaya Ramachandran, Olatunji Ruwase, Michael Ryan, Evangelos Vlachos posted to isca2008 by cfallin on 2009-05-29 23:50:25 as
	SimFlex: Statistical Sampling of Computer System Simulation [My Copy] IEEE Micro, Vol. 26, No. 4. (July 2006), pp. 18-31. by Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe posted to no-tag by cfallin on 2009-05-29 23:41:09 as along with 2 people hannibal_07 meisner
	The design and implementation of a first-generation CELL processor [My Copy] Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International (2005), pp. 184-592 Vol. 1. by D. Pham, S. Asano, M. Bolliger, et al.M. N. Day, H. P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Riley, D. Shippy, D. Stasiak, M. Suzuoki, M. Wang, J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, K. Yazawa posted to no-tag by cfallin on 2009-05-29 23:08:49 as along with 3 people kroatiker sprite ashwinma
	Thousand core chips: a technology perspective [My Copy] In DAC '07: Proceedings of the 44th annual Design Automation Conference (2007), pp. 746-749. by Shekhar Borkar posted to no-tag by cfallin on 2009-05-29 23:05:43 as along with 1 person akhi3030
	MIRA: A Multi-layered On-Chip Interconnect Router Architecture [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 251-261. by Dongkook Park, Soumya Eachempati, Reetuparna Das, et al.Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das posted to isca2008 by cfallin on 2009-05-28 05:40:55 as
	3D-Stacked Memory Architectures for Multi-core Processors [My Copy] Computer Architecture, 2008. ISCA '08. 35th International Symposium on In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (15 July 2008), pp. 453-464. by G. H. Loh posted to isca2008 by cfallin on 2009-05-28 05:32:36 as along with 2 people c_hughes jjm7673
	Atom-Aid: Detecting and Surviving Atomicity Violations [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 277-288. by Brandon Lucia, Joseph Devietti, Karin Strauss, Luis Ceze posted to isca2008 by cfallin on 2009-05-28 05:32:15 as
	Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 229-240. by Natalie E. Jerger, Li S. Peh, Mikko Lipasti posted to isca2008 by cfallin on 2009-05-28 05:31:49 as
	iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 241-250. by Avinash K. Kodi, Ashwini Sarathy, Ahmed Louri posted to isca2008 by cfallin on 2009-05-28 05:28:48 as
	Counting Dependence Predictors [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 215-226. by Franziska Roesner, Doug Burger, Stephen W. Keckler posted to isca2008 by cfallin on 2009-05-28 05:28:13 as
	Flexible Decoupled Transactional Memory Support [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 139-150. by Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott posted to isca2008 by cfallin on 2009-05-28 05:27:38 as
	TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 127-138. by Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood posted to isca2008 by cfallin on 2009-05-28 05:27:13 as
	Using Hardware Memory Protection to Build a High-Performance, Strongly-Atomic Hybrid Transactional Memory [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 115-126. by Lee Baugh, Naveen Neelakantam, Craig Zilles posted to isca2008 by cfallin on 2009-05-28 05:26:53 as
	Polymorphic On-Chip Networks [My Copy] Computer Architecture, International Symposium on, Vol. 0 (2008), pp. 101-112. by Martha M. Kim, John D. Davis, Mark Oskin, Todd Austin posted to isca2008 by cfallin on 2009-05-28 05:26:29 as
	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 89-100. by Jae W. Lee, Man C. Ng, Krste Asanovic posted to isca2008 by cfallin on 2009-05-28 05:26:05 as
	Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 63-74. by Onur Mutlu, Thomas Moscibroda posted to isca2008 by cfallin on 2009-05-28 05:25:37 as
	A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies [My Copy] In ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture (2008), pp. 51-62. by Shyamkumar Thoziyoor, Jung H. Ahn, Matteo Monchiero, Jay B. Brockman, Norman P. Jouppi posted to isca2008 by cfallin on 2009-05-28 05:20:12 as
	Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 337-348. by Robert D. Cameron, Dan Lin posted to asplos2009 by cfallin on 2009-05-28 05:11:47 as along with 1 person JoeVinegar
	Producing wrong data without doing anything obviously wrong! [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 265-276. by Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, Peter F. Sweeney posted to asplos2009 by cfallin on 2009-05-28 05:11:05 as along with 5 people mitake Gorzomagnificent akhi3030 pedagand myui
	Accelerating critical section execution with asymmetric multi-core architectures [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 253-264. by Aater M. Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt posted to asplos2009 by cfallin on 2009-05-28 05:10:46 as
	Dynamic prediction of collection yield for managed runtimes [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 289-300. by Michal Wegiel, Chandra Krintz posted to asplos2009 by cfallin on 2009-05-28 05:10:34 as
	Leak pruning [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 277-288. by Michael D. Bond, Kathryn S. Mckinley posted to asplos2009 by cfallin on 2009-05-28 05:10:18 as
	PowerNap: eliminating server idle power [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 205-216. by David Meisner, Brian T. Gold, Thomas F. Wenisch posted to asplos2009 by cfallin on 2009-05-28 05:10:06 as along with 3 people ehofer mrt2k9 sachingarg
	Early experience with a commercial hardware transactional memory implementation [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 157-168. by Dave Dice, Yossi Lev, Mark Moir, Daniel Nussbaum posted to asplos2009 by cfallin on 2009-05-28 05:10:00 as
	CTrigger: exposing atomicity violation bugs from their hiding places [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 25-36. by Soyeon Park, Shan Lu, Yuanyuan Zhou posted to asplos2009 by cfallin on 2009-05-28 05:06:07 as along with 2 people jahwa rhishi
	DMP: deterministic shared memory multiprocessing [My Copy] In ASPLOS '09: Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (2009), pp. 85-96. by Joseph Devietti, Brandon Lucia, Luis Ceze, Mark Oskin posted to asplos2009 by cfallin on 2009-05-28 05:04:41 as along with 2 people muli cometyang
	Efficient unicast and multicast support for CMPs [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 364-375. by S. Rodrigo, J. Flich, J. Duato, M. Hummel posted to micro2008 by cfallin on 2009-05-28 04:58:04 as along with 1 person yeminjiao
	Adaptive data compression for high-performance low-power on-chip networks [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 354-363. by Yuho Jin, Ki H. Yum, Eun J. Kim posted to micro2008 by cfallin on 2009-05-28 04:57:41 as along with 1 person yeminjiao
	Token flow control [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 342-353. by A. Kumar, L. S. Peh, N. K. Jha posted to micro2008 by cfallin on 2009-05-28 04:57:03 as along with 1 person yeminjiao
	Copy or Discard execution model for speculative parallelization on multicores [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 330-341. by Chen Tian, Min Feng, V. Nagarajan, R. Gupta posted to micro2008 by cfallin on 2009-05-28 04:54:51 as along with 1 person yeminjiao
	Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 318-329. by R. Bitirgen, E. Ipek, J. F. Martinez posted to micro2008 by cfallin on 2009-05-28 04:52:41 as along with 2 people yeminjiao mamadoudiao
	A performance-correctness explicitly-decoupled architecture [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 306-317. by A. Garg, M. C. Huang posted to micro2008 by cfallin on 2009-05-28 04:42:52 as along with 1 person yeminjiao
	Verification of chip multiprocessor memory systems using a relaxed scoreboard [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (2008), pp. 294-305. by O. Shacham, M. Wachs, A. Solomatnikov, A. Firoozshahian, S. Richardson, M. Horowitz posted to micro2008 by cfallin on 2009-05-28 04:41:34 as
	Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer [My Copy] Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on (12 November 2008), pp. 258-269. by L. Soares, D. Tam, M. Stumm posted to micro2008 by cfallin on 2009-05-28 04:40:43 as along with 1 person yeminjiao

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