Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security Export

@incollection{guo09pairing-coproc, abstract = {Elliptic Curve Cryptography implementations are known to be vulnerable to various side-channel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of side-channel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security.}, author = {Guo, Xu and Fan, Junfeng and Schaumont, Patrick and Verbauwhede, Ingrid}, citeulike-article-id = {5804593}, citeulike-linkout-0 = {http://dx.doi.org/10.1007/978-3-642-04138-9_21}, citeulike-linkout-1 = {http://www.springerlink.com/content/9869504723r6qru5}, doi = {10.1007/978-3-642-04138-9_21}, journal = {Cryptographic Hardware and Embedded Systems - CHES 2009}, keywords = {kungschool}, pages = {289--303}, posted-at = {2009-09-19 05:37:20}, priority = {2}, title = {Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security}, url = {http://dx.doi.org/10.1007/978-3-642-04138-9_21}, year = {2009} }

TY - CHAP ID - guo09pairing-coproc L3 - citeulike-article-id:5804593 N2 - Elliptic Curve Cryptography implementations are known to be vulnerable to various side-channel attacks and fault injection attacks, and many countermeasures have been proposed. However, selecting and integrating a set of countermeasures targeting multiple attacks into an ECC design is far from trivial. Security, performance and cost need to be considered together. In this paper, we describe a generic ECC coprocessor architecture, which is scalable and programmable. We demonstrate the coprocessor architecture with a set of countermeasures to address a collection of side-channel attacks and fault attacks. The programmable design of the coprocessor enables tradeoffs between area, speed, and security. JF - Cryptographic Hardware and Embedded Systems - CHES 2009 EP - 303 TI - Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security SP - 289 KW - kungschool AU - Guo, Xu AU - Fan, Junfeng AU - Schaumont, Patrick AU - Verbauwhede, Ingrid PY - 2009/// UR - http://dx.doi.org/10.1007/978-3-642-04138-9_21 ER -