Double precision floating-point arithmetic on FPGAs Export

by: S. Paschalakis, P. Lee

Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on (22 March 2004), pp. 352-358.

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Abstract

We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling.

@inproceedings{citeulike:5998179, abstract = {We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling.}, author = {Paschalakis, S. and Lee, P.}, citeulike-article-id = {5998179}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/FPT.2003.1275775}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1275775}, day = {22}, doi = {10.1109/FPT.2003.1275775}, journal = {Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on}, keywords = {dsp, fpga}, month = {March}, pages = {352--358}, posted-at = {2009-11-05 09:49:53}, priority = {2}, title = {Double precision floating-point arithmetic on FPGAs}, url = {http://dx.doi.org/10.1109/FPT.2003.1275775}, year = {2004} }

RIS record

TY - CONF ID - citeulike:5998179 L3 - citeulike-article-id:5998179 N2 - We present low cost FPGA floating-point arithmetic circuits for all the common operations, i.e. addition/subtraction, multiplication, division and square root. Such circuits can be extremely useful in the FPGA implementation of complex systems that benefit from the reprogrammability and parallelism of the FPGA device but also require a general purpose arithmetic unit. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 64-bit double precision circuits that also provide rounding and exception handling. JF - Field-Programmable Technology (FPT), 2003. Proceedings. 2003 IEEE International Conference on EP - 358 TI - Double precision floating-point arithmetic on FPGAs SP - 352 KW - dsp KW - fpga AU - Paschalakis, S AU - Lee, P PY - 2004/03/22/ UR - http://dx.doi.org/10.1109/FPT.2003.1275775 ER -

Double precision floating-point arithmetic on FPGAs Export

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