The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock Export

@article{citeulike:6055588, abstract = {The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture, In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC's 0.6 \μm SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns}, author = {Chiang, Jen-Shiun and Chen, Kuang-Yuan}, citeulike-article-id = {6055588}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/82.775392}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=775392}, day = {06}, doi = {10.1109/82.775392}, journal = {Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on}, keywords = {digital, pll}, month = {August}, number = {7}, pages = {945--950}, posted-at = {2009-11-02 08:31:45}, priority = {2}, title = {The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock}, url = {http://dx.doi.org/10.1109/82.775392}, volume = {46}, year = {2002} }

TY - JOUR ID - citeulike:6055588 L3 - citeulike-article-id:6055588 N2 - The cores of the all-digital phase-locked loop (ADPLL) are the switch-tuning digital control oscillator (DCO) and the architecture, In this brief, we propose a DCO with reduced hardware cost, and architecture with characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high-performance microprocessors. The prototype of a 3.3-V ADPLL chip has been designed by TSMC's 0.6 μm SPDM CMOS process. The simulation shows that this ADPLL can operate in the range between 60 and 400 MHz, and at four times the reference clock frequency. The phase-lock process takes 47 clock cycles, and the phase error is less than 0.1 ns IS - 7 JF - Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on EP - 950 TI - The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock VL - 46 SP - 945 KW - digital KW - pll AU - Chiang, Jen-Shiun AU - Chen, Kuang-Yuan PY - 2002/08/06/ UR - http://dx.doi.org/10.1109/82.775392 ER -