A low-noise fast-lock phase-locked loop with adaptive bandwidth control Export

@article{citeulike:6055600, abstract = {This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50\% duty cycle ratio over all operating frequency range}, author = {Lee, Joonsuk and Kim, Beomsup}, citeulike-article-id = {6055600}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/4.859502}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=859502}, day = {06}, doi = {10.1109/4.859502}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {pll}, month = {August}, number = {8}, pages = {1137--1145}, posted-at = {2009-11-02 08:38:19}, priority = {2}, title = {A low-noise fast-lock phase-locked loop with adaptive bandwidth control}, url = {http://dx.doi.org/10.1109/4.859502}, volume = {35}, year = {2002} }

TY - JOUR ID - citeulike:6055600 L3 - citeulike-article-id:6055600 N2 - This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range IS - 8 JF - Solid-State Circuits, IEEE Journal of EP - 1145 TI - A low-noise fast-lock phase-locked loop with adaptive bandwidth control VL - 35 SP - 1137 KW - pll AU - Lee, Joonsuk AU - Kim, Beomsup PY - 2002/08/06/ UR - http://dx.doi.org/10.1109/4.859502 ER -