Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array Export

@inproceedings{citeulike:6080599, abstract = {This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed.}, author = {Green, P. J. and Taylor, D. P.}, citeulike-article-id = {6080599}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/DELTA.2006.56}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1581193}, day = {30}, doi = {10.1109/DELTA.2006.56}, journal = {Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on}, keywords = {fpga, receiver, sdr}, month = {January}, pages = {4 pp.+}, posted-at = {2009-11-06 12:19:33}, priority = {2}, title = {Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array}, url = {http://dx.doi.org/10.1109/DELTA.2006.56}, year = {2006} }

TY - CONF ID - citeulike:6080599 L3 - citeulike-article-id:6080599 N2 - This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be implemented on a Xilinx Virtex 2 pro field programmable gate array. It is designed and developed for research into receiver diversity and multiple input and multiple output (MIMO) wireless systems. Each receiver has a freescale DSP56321 digital signal processor (DSP) to run synchronization, channel state estimation and equalization algorithms. The system is software defined to allow for flexibility in the choice of receiver demodulation formats, output data rates and space-time decoding schemes. Hardware, firmware and software aspects of the receiver and space time decoder system to meet design requirements are discussed. JF - Electronic Design, Test and Applications, 2006. DELTA 2006. Third IEEE International Workshop on TI - Implementation of four real-time software defined receivers and a space-time decoder using Xilinx Virtex 2 pro field programmable gate array SP - 4 pp. KW - fpga KW - receiver KW - sdr AU - Green, PJ AU - Taylor, DP PY - 2006/01/30/ UR - http://dx.doi.org/10.1109/DELTA.2006.56 ER -