An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS Export

@inproceedings{Vangal0780Tile, abstract = {A 275mm² network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.}, author = {Vangal, S. and Howard, J. and Ruhl, G. and Dighe, S. and Wilson, H. and Tschanz, J. and Finan, D. and Iyer, P. and Singh, A. and Singh, A. and Jacob, T. and A10 and Jain, S. and A11 and Venkataraman, S. and A12 and Hoskote, Y. and A13 and Borkar, N. and A14}, booktitle = {Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International}, citeulike-article-id = {2692630}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/ISSCC.2007.373606}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4242283}, doi = {10.1109/ISSCC.2007.373606}, journal = {Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International}, keywords = {65nm, high-performance, hpc, many-core, multi-core}, pages = {98--589}, posted-at = {2008-04-20 11:10:26}, priority = {2}, title = {An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS}, url = {http://dx.doi.org/10.1109/ISSCC.2007.373606}, year = {2007} }

TY - CONF ID - Vangal0780Tile L3 - citeulike-article-id:2692630 N2 - A 275mm² network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W. JF - Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International EP - 589 TI - An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS T2 - Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International SP - 98 KW - 65nm KW - high-performance KW - hpc KW - many-core KW - multi-core AU - Vangal, S AU - Howard, J AU - Ruhl, G AU - Dighe, S AU - Wilson, H AU - Tschanz, J AU - Finan, D AU - Iyer, P AU - Singh, A AU - Singh, A AU - Jacob, T AU - A10 AU - Jain, S AU - A11 AU - Venkataraman, S AU - A12 AU - Hoskote, Y AU - A13 AU - Borkar, N AU - A14 PY - 2007/// UR - http://dx.doi.org/10.1109/ISSCC.2007.373606 ER -