A fully integrated SOC for 802.11b in 0.18-μm CMOS Export

@article{citeulike:5034133, abstract = {A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-\μm CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range.}, author = {Khorram, S. and Darabi, H. and Zhou, Zhimin and Li, Qiang and Marholev, B. and Chiu, J. and Castaneda, J. and Chien, Hung-Ming and Anand, S. B. and Wu, S. and Pan, Meng-An and Roofougaran, R. and Kim, Hea J. and Lettieri, P. and Ibrahim, B. and Rael, J. J. and Tran, L. H. and Geronaga, E. and Yeh, H. and Frost, T. and Trachewsky, J. and Rofougaran, A.}, booktitle = {Solid-State Circuits, IEEE Journal of}, citeulike-article-id = {5034133}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/JSSC.2005.857419}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1546225}, doi = {10.1109/JSSC.2005.857419}, journal = {Solid-State Circuits, IEEE Journal of}, keywords = {80211b, 80211g, cmos, radio, receiver, soc, transceiver}, number = {12}, pages = {2492--2501}, posted-at = {2009-07-01 16:27:51}, priority = {2}, title = {A fully integrated SOC for 802.11b in 0.18-\μm CMOS}, url = {http://dx.doi.org/10.1109/JSSC.2005.857419}, volume = {40}, year = {2005} }

TY - JOUR ID - citeulike:5034133 L3 - citeulike-article-id:5034133 N2 - A fully integrated system-on-a-chip (SOC) intended for use in 802.11b applications is built in 0.18-μm CMOS. All of the radio building blocks including the power amplifier (PA), the phase-locked loop (PLL) filter, and the antenna switch, as well as the complete baseband physical layer and the medium access control (MAC) sections, have been integrated into a single chip. The radio tuned to 2.4 GHz dissipates 165 mW in the receive mode and 360 mW in the transmit mode from a 1.8-V supply. The receiver achieves a typical noise figure of 6 dB and -88-dBm sensitivity at 11 Mb/s rate. The transmitter delivers a nominal output power of 13 dBm at the antenna. The transmitter 1-dB compression point is 18 dBm and has over 20 dB of gain range. IS - 12 JF - Solid-State Circuits, IEEE Journal of EP - 2501 TI - A fully integrated SOC for 802.11b in 0.18-μm CMOS VL - 40 T2 - Solid-State Circuits, IEEE Journal of SP - 2492 KW - 80211b KW - 80211g KW - cmos KW - radio KW - receiver KW - soc KW - transceiver AU - Khorram, S AU - Darabi, H AU - Zhou, Zhimin AU - Li, Qiang AU - Marholev, B AU - Chiu, J AU - Castaneda, J AU - Chien, Hung-Ming AU - Anand, SB AU - Wu, S AU - Pan, Meng-An AU - Roofougaran, R AU - Kim, Hea AU - Lettieri, P AU - Ibrahim, B AU - Rael, JJ AU - Tran, LH AU - Geronaga, E AU - Yeh, H AU - Frost, T AU - Trachewsky, J AU - Rofougaran, A PY - 2005/// UR - http://dx.doi.org/10.1109/JSSC.2005.857419 ER -