FPGA Implementation of Carrier Synchronization for QAM Receivers Export

@article{citeulike:618124, abstract = {Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator™ for DSP described.}, address = {Hingham, MA, USA}, author = {Dick, Chris and Harris, Fred and Rice, Michael}, citeulike-article-id = {618124}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=960097}, citeulike-linkout-1 = {http://dx.doi.org/10.1023/B:VLSI.0000008070.30837.e1}, doi = {10.1023/B:VLSI.0000008070.30837.e1}, issn = {0922-5773}, journal = {J. VLSI Signal Process. Syst.}, keywords = {carrier-synchronization, fpga, qam, receiver, sdr, synchronization}, month = {January}, number = {1}, pages = {57--71}, posted-at = {2009-06-26 19:32:08}, priority = {2}, publisher = {Kluwer Academic Publishers}, title = {FPGA Implementation of Carrier Synchronization for QAM Receivers}, url = {http://dx.doi.org/10.1023/B:VLSI.0000008070.30837.e1}, volume = {36}, year = {2004} }

TY - JOUR ID - citeulike:618124 L3 - citeulike-article-id:618124 N2 - Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. While there are a number of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and flexibility. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper examines carrier synchronization in SDRs using FPGA based signal processors. We provide a tutorial style overview of carrier recovery techniques for QPSK and QAM modulation schemes and report on the design and FPGA implementation of a carrier recovery loop for a 16-QAM modern. Two design alternatives are presented to highlight the rich design space accessible using configurable logic. The FPGA device utilization and performance for a carrier recovery circuit using a look-up table approach and CORDIC arithmetic are presented. The simulation and FPGA implementation process using a recent system level design tool called System Generator™ for DSP described. IS - 1 JF - J. VLSI Signal Process. Syst. SN - 0922-5773 AD - Hingham, MA, USA EP - 71 TI - FPGA Implementation of Carrier Synchronization for QAM Receivers PB - Kluwer Academic Publishers VL - 36 SP - 57 KW - carrier-synchronization KW - fpga KW - qam KW - receiver KW - sdr KW - synchronization AU - Dick, Chris AU - Harris, Fred AU - Rice, Michael PY - 2004/01// UR - http://dx.doi.org/10.1023/B:VLSI.0000008070.30837.e1 ER -