Automated custom instruction generation for domain-specific processor acceleration Export

@article{citeulike:4746762, abstract = {Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or coprocessors), and the corresponding instructions are added to a baseline processor to meet the critical computational demands of a target application. In this paper, the design of a system to automate the instruction set customization process is presented. A dataflow graph design space exploration engine efficiently identifies computation subgraphs to create custom hardware and a compiler subgraph matching framework seamlessly exploits this hardware. We demonstrate the effectiveness of this system across a range of application domains and study the applicability of the custom hardware across an entire application domain. Generalization techniques are presented which enable the application-specific hardware to be more effectively used across a domain.}, author = {Clark, N. T. and Zhong, H. and Mahlke, S. A.}, booktitle = {Computers, IEEE Transactions on}, citeulike-article-id = {4746762}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TC.2005.156}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1501791}, comment = {Good source of background on prior work in utilizing ISA extensions.}, doi = {10.1109/TC.2005.156}, journal = {Computers, IEEE Transactions on}, keywords = {accelerators, architecture, compiler, dfg, eda}, number = {10}, pages = {1258--1270}, posted-at = {2009-06-04 23:36:22}, priority = {2}, title = {Automated custom instruction generation for domain-specific processor acceleration}, url = {http://dx.doi.org/10.1109/TC.2005.156}, volume = {54}, year = {2005} }

TY - JOUR ID - citeulike:4746762 L3 - citeulike-article-id:4746762 N2 - Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded applications. Hardware, in the form of new function units (or coprocessors), and the corresponding instructions are added to a baseline processor to meet the critical computational demands of a target application. In this paper, the design of a system to automate the instruction set customization process is presented. A dataflow graph design space exploration engine efficiently identifies computation subgraphs to create custom hardware and a compiler subgraph matching framework seamlessly exploits this hardware. We demonstrate the effectiveness of this system across a range of application domains and study the applicability of the custom hardware across an entire application domain. Generalization techniques are presented which enable the application-specific hardware to be more effectively used across a domain. IS - 10 JF - Computers, IEEE Transactions on EP - 1270 TI - Automated custom instruction generation for domain-specific processor acceleration VL - 54 T2 - Computers, IEEE Transactions on SP - 1258 KW - accelerators KW - architecture KW - compiler KW - dfg KW - eda N1 - Good source of background on prior work in utilizing ISA extensions. AU - Clark, NT AU - Zhong, H AU - Mahlke, SA PY - 2005/// UR - http://dx.doi.org/10.1109/TC.2005.156 ER -