An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors Export

@inproceedings{citeulike:4816908, abstract = {Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency along critical paths and reduces the number of intermediate results stored in the register file. While custom instructions can be effective, the time and cost of designing a new processor for each application is immense. To overcome this roadblock, this paper proposes a flexible architectural framework to transparently integrate custom instructions into a general-purpose processor. Hardware accelerators are added to the processor to execute the collapsed subgraphs. A simple microarchitectural interface is provided to support a plug-and-play model for integrating a wide range of accelerators into a pre-designed and verified processor core. The accelerators are exploited using an approach of static identification and dynamic realization. The compiler is responsible for identifying profitable subgraphs, while the hardware handles discovery, mapping, and execution of compatible subgraphs. This paper presents the design of a plug-and-play transparent accelerator system and evaluates the cost/performance implications of the design.}, address = {Washington, DC, USA}, author = {Clark, Nathan and Blome, Jason and Chu, Michael and Mahlke, Scott and Biles, Stuart and Flautner, Krisztian}, booktitle = {ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture}, citeulike-article-id = {4816908}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=1069807.1069993}, citeulike-linkout-1 = {http://dx.doi.org/10.1109/ISCA.2005.9}, doi = {10.1109/ISCA.2005.9}, isbn = {0-7695-2270-X}, keywords = {accelerators, architecture, compiler, embedded}, pages = {272--283}, posted-at = {2009-06-11 22:34:06}, priority = {2}, publisher = {IEEE Computer Society}, title = {An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors}, url = {http://dx.doi.org/10.1109/ISCA.2005.9}, year = {2005} }

TY - CONF ID - citeulike:4816908 L3 - citeulike-article-id:4816908 N2 - Instruction set customization is an effective way to improve processor performance. Critical portions of applicationdata-flow graphs are collapsed for accelerated execution on specialized hardware. Collapsing dataflow subgraphs will compress the latency along critical paths and reduces the number of intermediate results stored in the register file. While custom instructions can be effective, the time and cost of designing a new processor for each application is immense. To overcome this roadblock, this paper proposes a flexible architectural framework to transparently integrate custom instructions into a general-purpose processor. Hardware accelerators are added to the processor to execute the collapsed subgraphs. A simple microarchitectural interface is provided to support a plug-and-play model for integrating a wide range of accelerators into a pre-designed and verified processor core. The accelerators are exploited using an approach of static identification and dynamic realization. The compiler is responsible for identifying profitable subgraphs, while the hardware handles discovery, mapping, and execution of compatible subgraphs. This paper presents the design of a plug-and-play transparent accelerator system and evaluates the cost/performance implications of the design. SN - 0-7695-2270-X AD - Washington, DC, USA EP - 283 TI - An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors PB - IEEE Computer Society T2 - ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture SP - 272 KW - accelerators KW - architecture KW - compiler KW - embedded AU - Clark, Nathan AU - Blome, Jason AU - Chu, Michael AU - Mahlke, Scott AU - Biles, Stuart AU - Flautner, Krisztian PY - 2005/// UR - http://dx.doi.org/10.1109/ISCA.2005.9 ER -