Next generation Intel® micro-architecture (Nehalem) clocking architecture Export

@inproceedings{citeulike:5826589, abstract = {This paper describes the next generation Intel^reg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intel^reg QuickPath interconnect and Intel^reg QuickPath memory controller clock generation, and jitter-attenuating DLLs.}, author = {Kurd, N. and Douglas, J. and Mosalikanti, P. and Kumar, R.}, citeulike-article-id = {5826589}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/VLSIC.2008.4585952}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4585952}, day = {01}, doi = {10.1109/VLSIC.2008.4585952}, journal = {VLSI Circuits, 2008 IEEE Symposium on}, keywords = {architecture}, month = {August}, pages = {62--63}, posted-at = {2009-09-23 01:28:41}, priority = {2}, title = {Next generation Intel\&\#x00AE; micro-architecture (Nehalem) clocking architecture}, url = {http://dx.doi.org/10.1109/VLSIC.2008.4585952}, year = {2008} }

TY - CONF ID - citeulike:5826589 L3 - citeulike-article-id:5826589 N2 - This paper describes the next generation Intel^reg micro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter Intel^reg QuickPath interconnect and Intel^reg QuickPath memory controller clock generation, and jitter-attenuating DLLs. JF - VLSI Circuits, 2008 IEEE Symposium on EP - 63 TI - Next generation Intel® micro-architecture (Nehalem) clocking architecture SP - 62 KW - architecture AU - Kurd, N AU - Douglas, J AU - Mosalikanti, P AU - Kumar, R PY - 2008/08/01/ UR - http://dx.doi.org/10.1109/VLSIC.2008.4585952 ER -