Microarchitectural techniques for power gating of execution units Export

@inproceedings{citeulike:803309, abstract = {Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28\% of the execution cycles at a performance loss of 2\%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40\% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.}, address = {New York, NY, USA}, author = {Hu, Zhigang and Buyuktosunoglu, Alper and Srinivasan, Viji and Zyuban, Victor and Jacobson, Hans and Bose, Pradip}, booktitle = {ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design}, citeulike-article-id = {803309}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=1013249}, citeulike-linkout-1 = {http://dx.doi.org/10.1145/1013235.1013249}, doi = {10.1145/1013235.1013249}, isbn = {1-58113-929-2}, keywords = {architecture, management, power}, location = {Newport Beach, California, USA}, pages = {32--37}, posted-at = {2009-09-23 01:33:05}, priority = {2}, publisher = {ACM}, title = {Microarchitectural techniques for power gating of execution units}, url = {http://dx.doi.org/10.1145/1013235.1013249}, year = {2004} }

TY - CONF ID - citeulike:803309 L3 - citeulike-article-id:803309 N2 - Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units. CY - Newport Beach, California, USA SN - 1-58113-929-2 AD - New York, NY, USA EP - 37 TI - Microarchitectural techniques for power gating of execution units PB - ACM T2 - ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design SP - 32 KW - architecture KW - management KW - power AU - Hu, Zhigang AU - Buyuktosunoglu, Alper AU - Srinivasan, Viji AU - Zyuban, Victor AU - Jacobson, Hans AU - Bose, Pradip PY - 2004/// UR - http://dx.doi.org/10.1145/1013235.1013249 ER -