A system for synthesizing optimized FPGA hardware from Matlab(R) Export

@proceedings{citeulike:1081932, abstract = {Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware}, author = {Haldar, M. and Nayak, A. and Choudhary, A. and Banerjee, P.}, citeulike-article-id = {1081932}, citeulike-linkout-0 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=968639}, journal = {Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on}, keywords = {eusipco07}, pages = {314--319}, posted-at = {2007-02-01 11:32:21}, priority = {2}, title = {A system for synthesizing optimized FPGA hardware from Matlab(R)}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=968639}, year = {2001} }

TY - CONF ID - citeulike:1081932 L3 - citeulike-article-id:1081932 N2 - Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computations and meet time-to-market pressures. We present a compiler that takes as input algorithms described in MATLAB and generates RTL VHDL. The RTL VHDL then can be mapped to FPGAs using existing commercial tools. The input application is mapped to multiple FPGAs by parallelizing the application and embedding communication and synchronization primitives automatically. Our compiler infers the minimum number of bits required to represent the variable through a precision analysis framework. The compiler can leverage optimized IP cores to enhance the hardware generated. The compiler also exploits parallelism in the input algorithm by pipelining in the presence of resource constraints. We demonstrate the utility of the compiler by synthesizing hardware for a couple of signal/image processing algorithms and comparing them with manually designed hardware JF - Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on EP - 319 TI - A system for synthesizing optimized FPGA hardware from Matlab(R) SP - 314 KW - eusipco07 AU - Haldar, M AU - Nayak, A AU - Choudhary, A AU - Banerjee, P PY - 2001/// UR - http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=968639 ER -