Vector LLVA: a virtual vector instruction set for media processing Export

@inproceedings{citeulike:5486967, abstract = {We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-specific parameters. We provide both arbitrary-length vectors (for targets that allow vectors of arbitrary length, or where the target length is not known) and fixed-length vectors (for targets that have a fixed vector length, such as subword SIMD extensions), together with a rich set of operations on both vector types. We have implemented translators that compile (1) Vector LLVA written with arbitrary-length vectors to the Motorola RSVP architecture and (2) Vector LLVA written with fixed-length vectors to both AltiVec and Intel SSE2. Our translatorgenerated code achieves speedups competitive with handwritten native code versions of several benchmarks on all three architectures. These experiments show that our V-ISA design captures vector parallelism for two quite different classes of architectures and provides virtual object code portability within the class of subword SIMD architectures.}, address = {New York, NY, USA}, author = {Bocchino, Robert L. and Adve, Vikram S.}, booktitle = {VEE '06: Proceedings of the 2nd international conference on Virtual execution environments}, citeulike-article-id = {5486967}, citeulike-linkout-0 = {http://portal.acm.org/citation.cfm?id=1134769}, citeulike-linkout-1 = {http://dx.doi.org/10.1145/1134760.1134769}, doi = {10.1145/1134760.1134769}, isbn = {1-59593-332-6}, keywords = {llvm, vj}, location = {Ottawa, Ontario, Canada}, pages = {46--56}, posted-at = {2009-08-19 16:29:04}, priority = {2}, publisher = {ACM}, title = {Vector LLVA: a virtual vector instruction set for media processing}, url = {http://dx.doi.org/10.1145/1134760.1134769}, year = {2006} }

TY - CONF ID - citeulike:5486967 L3 - citeulike-article-id:5486967 N2 - We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-specific parameters. We provide both arbitrary-length vectors (for targets that allow vectors of arbitrary length, or where the target length is not known) and fixed-length vectors (for targets that have a fixed vector length, such as subword SIMD extensions), together with a rich set of operations on both vector types. We have implemented translators that compile (1) Vector LLVA written with arbitrary-length vectors to the Motorola RSVP architecture and (2) Vector LLVA written with fixed-length vectors to both AltiVec and Intel SSE2. Our translatorgenerated code achieves speedups competitive with handwritten native code versions of several benchmarks on all three architectures. These experiments show that our V-ISA design captures vector parallelism for two quite different classes of architectures and provides virtual object code portability within the class of subword SIMD architectures. CY - Ottawa, Ontario, Canada SN - 1-59593-332-6 AD - New York, NY, USA EP - 56 TI - Vector LLVA: a virtual vector instruction set for media processing PB - ACM T2 - VEE '06: Proceedings of the 2nd international conference on Virtual execution environments SP - 46 KW - llvm KW - vj AU - Bocchino, Robert AU - Adve, Vikram PY - 2006/// UR - http://dx.doi.org/10.1145/1134760.1134769 ER -