Shared Memory Consistency Models: A Tutorial Export

@article{citeulike:5916345, abstract = {Parallel systems that support the shared memory abstraction are becoming widely accepted in many areas of computing. Writing correct and efficient programs for such systems requires a formal specification of memory semantics, called a memory consistency model. The most intuitive model---sequential consistency---greatly restricts the use of many performance optimizations commonly used by uniprocessor hardware and compiler designers, thereby reducing the benefit of using a multiprocessor. To alleviate this problem, many current multiprocessors support more relaxed consistency models. Unfortunately, the models supported by various systems differ from each other in subtle yet important ways. Furthermore, precisely defining the semantics of each model often leads to complex specifications that are difficult to understand for typical users and builders of computer systems. The purpose of this tutorial paper is to describe issues related to memory consistency models in a way that would be un...}, author = {Adve, Sarita V. and Gharachorloo, Kourosh}, citeulike-article-id = {5916345}, citeulike-linkout-0 = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.53.4665}, journal = {IEEE Computer}, keywords = {dsm, memory\_consistency}, pages = {66--76}, posted-at = {2009-10-09 15:28:50}, priority = {0}, title = {Shared Memory Consistency Models: A Tutorial}, url = {http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.53.4665}, volume = {29}, year = {1995} }

TY - JOUR ID - citeulike:5916345 L3 - citeulike-article-id:5916345 N2 - Parallel systems that support the shared memory abstraction are becoming widely accepted in many areas of computing. Writing correct and efficient programs for such systems requires a formal specification of memory semantics, called a memory consistency model. The most intuitive model---sequential consistency---greatly restricts the use of many performance optimizations commonly used by uniprocessor hardware and compiler designers, thereby reducing the benefit of using a multiprocessor. To alleviate this problem, many current multiprocessors support more relaxed consistency models. Unfortunately, the models supported by various systems differ from each other in subtle yet important ways. Furthermore, precisely defining the semantics of each model often leads to complex specifications that are difficult to understand for typical users and builders of computer systems. The purpose of this tutorial paper is to describe issues related to memory consistency models in a way that would be un... JF - IEEE Computer EP - 76 TI - Shared Memory Consistency Models: A Tutorial VL - 29 SP - 66 KW - dsm KW - memory_consistency AU - Adve, Sarita AU - Gharachorloo, Kourosh PY - 1995/// UR - http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.53.4665 ER -