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jmmcg's publications [12 articles]

 
 

A DSEL for Addressing the Problems Posed by Parallel Architectures

  [CiTO]
Overload, No. 111. (October 2012), pp. 13-18
posted to accu cxx dataflow dsel overload parallel software threading by jmmcg on 2012-11-22 00:16:24 read
 

Implementing Batcher’s Bitonic Sort in C++: An Investigation into using Library-Based, Data-Parallelism Support in C++.

  [CiTO]
In The Leslie Comrie Seminar Series (5 October 2011)
posted to batchers bitonic cxx dataflow parallel software sort stl threading by jmmcg on 2012-11-21 23:56:33 read
 

Introducing Parallel Pixie Dust: Advanced Library-Based Support for Parallelism in C++

  [CiTO]
In Computer Science Research Colloquium (26 April 2011)
posted to cxx dataflow parallel software stl threading by jmmcg on 2012-11-21 23:47:54 read
 

Introducing Parallel Pixie Dust: Advanced Library-Based Support for Parallelism in C++

  [CiTO]
In Current Trends and Challenges in Distributed and Scalable Computing (14 April 2011)
posted to bcs computer cxx dataflow dsc parallel stl threading by jmmcg on 2012-11-21 23:38:40 read
 

Introducing Parallel Pixie Dust:Advanced Library-Based Support for Parallelism in C++

  [CiTO]
In BCS APSG (23 February 2011)
posted to bcs cxx dataflow parallel programming software stl threading by jmmcg on 2012-11-21 23:28:17 read
 

C++ Data-flow Parallelism sounds great! But how practical is it? Let’s see how well it works with the SPEC2006 benchmark suite.

  [CiTO]
In ACCU 2012 (April 2012)
posted to accu c computer cxx dataflow parallel software stl threading by jmmcg on 2012-11-21 23:19:24 read
 

Introducing Parallel Pixie Dust: A Novel C++ Threading Library

  [CiTO]
(22 April 2009)
posted to accu cxx parallel ppd threading by jmmcg on 2009-08-11 12:46:12 read

Abstract

Over recent years there has been considerable development of multi-core processors, which increase architectural performance by providing thread-level parallelism. To maximise the performance of software on those architectures, programmers would have to write their code to exploit that thread-level parallelism, implying knowledge of that hardware. But from the programmer view-point writing parallel code correctly and efficiently, for an underlying hardware, has been non-trivial.The usual library-based approach has been very problematic. In particular, locking has not been found to be composable, because ...

 

Massively Parallel Architectures

  [CiTO]
(August 2007)
posted to bcs cellular cyclops dimes gilgamesh iet parallel picochip pim shamrock by jmmcg on 2009-08-11 12:31:54 read
 

The Challenges of Writing Software for Massively Parallel Architectures.

  [CiTO]
(July 2005)
posted to cellular cyclops microgrid pim by jmmcg on 2009-08-11 12:20:18 read
 

The Challenges facing Libraries and Imperative Languages from Massively Parallel Architectures

  [CiTO]
(2 April 2008)
posted to accu cellular cyclops dimes parallel pim by jmmcg on 2009-04-28 18:06:34 read

Abstract

The challenges of writing programs for parallel architectures has become an ever more prescient in the light of the pervasiveness of desktop multi-core processors and readily available consumer grids. This may be seen as an effective increase in instruction retirement rate via the multiple cores of execution that have been made available to the programmer. This has, in turn, exacerbated the memory wall, the rate at which data can be read from and written to main memory via the various memory ...

 

The Challenges of Efficient Code-Generation for Massively Parallel Architectures

  [CiTO]
Advances in Computer Systems Architecture (2006), pp. 416-422, doi:10.1007/11859802_38
posted to cellular cyclops dimes parallel pim by jmmcg on 2009-04-28 17:45:59 read

Abstract

Overcoming the memory wall [15] may be achieved by increasing the bandwidth and reducing the latency of the processor to memory connection, for example by implementing Cellular architectures, such as the IBM Cyclops. Such massively parallel architectures have sophisticated memory models. In this paper we used DIMES (the Delaware Iterative Multiprocessor Emulation System), developed by CAPSL at the University of Delaware, as a hardware evaluation tool for cellular architectures. The authors contend that there is an open question regarding the potential, ...

 

Automatic Code-Generation Techniques for Micro-Threaded RISC Architectures

  [CiTO]
(July 2006)
posted to care cellular cyclops dimes parallel pim threading by jmmcg on 2009-04-28 17:41:32 read

Abstract

There has been an ever-widening gap between processor and memory speeds,resulting in a 'memory wall' where the time for memory accesses dominates performance. To counter this, architectures that use many very small threads that allow multiple memory accesses to occur in parallel have been under investigation. Examples of these architectures are the CARE (Compiler Aided Reorder Engine) architecture,micro-threading architectures and cellular architectures, such as the IBMCyclops family, implementing using processors-in-memory (PIM), which is the main architecture discussed in this thesis. PIM ...

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