Generating FPGA-Accelerated DFT Libraries Export

@inproceedings{citeulike:1755932, abstract = {We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision. The partitioning strategy is a heuristic based on the DFT's divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. We have integrated this approach in the Spiral linear-transform code-generation framework to support push-button automatic implementation. We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-II Pro FPGA. In our experiments, the 1D and 2D DFT's FPGA-accelerated libraries exhibit between 2 and 7.5 times higher performance (operations per second) and up to 2.5 times better energy efficiency (operations per Joule) than the software-only version.}, author = {D'Alberto, P. and Milder, P. A. and Sandryhaila, A. and Franchetti, F. and Hoe, J. C. and Moura, J. M. F. and Puschel, M. and Johnson, J. R.}, booktitle = {Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on}, citeulike-article-id = {1755932}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/FCCM.2007.58}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4297254}, day = {04}, doi = {10.1109/FCCM.2007.58}, journal = {Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on}, keywords = {dsp\_on\_fpga, fixedpoint, fpga, linear\_algebra, matrix, reconfigurable\_computing}, month = {September}, pages = {173--184}, posted-at = {2009-09-16 07:58:50}, priority = {2}, title = {Generating FPGA-Accelerated DFT Libraries}, url = {http://dx.doi.org/10.1109/FCCM.2007.58}, year = {2007} }

TY - CONF ID - citeulike:1755932 L3 - citeulike-article-id:1755932 N2 - We present a domain-specific approach to generate high-performance hardware-software partitioned implementations of the discrete Fourier transform (DFT) in fixed point precision. The partitioning strategy is a heuristic based on the DFT's divide-and-conquer algorithmic structure and fine tuned by the feedback-driven exploration of candidate designs. We have integrated this approach in the Spiral linear-transform code-generation framework to support push-button automatic implementation. We present evaluations of hardware-software DFT implementations running on the embedded PowerPC processor and the reconfigurable fabric of the Xilinx Virtex-II Pro FPGA. In our experiments, the 1D and 2D DFT's FPGA-accelerated libraries exhibit between 2 and 7.5 times higher performance (operations per second) and up to 2.5 times better energy efficiency (operations per Joule) than the software-only version. JF - Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on EP - 184 TI - Generating FPGA-Accelerated DFT Libraries T2 - Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on SP - 173 KW - dsp_on_fpga KW - fixedpoint KW - fpga KW - linear_algebra KW - matrix KW - reconfigurable_computing AU - D'Alberto, P AU - Milder, PA AU - Sandryhaila, A AU - Franchetti, F AU - Hoe, JC AU - Moura, JMF AU - Puschel, M AU - Johnson, JR PY - 2007/09/04/ UR - http://dx.doi.org/10.1109/FCCM.2007.58 ER -