Warp Processing: Dynamic Translation of Binaries to FPGA Circuits Export

@article{citeulike:3287556, abstract = {Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demonstrate warp processing's potential.}, author = {Vahid, F. and Stitt, G. and Lysecky, R.}, booktitle = {Computer}, citeulike-article-id = {3287556}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/MC.2008.240}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4563878}, doi = {10.1109/MC.2008.240}, journal = {Computer}, keywords = {compiler\_design, computer\_architecture, fpga, reconfigurable\_computing}, number = {7}, pages = {40--46}, posted-at = {2008-09-18 15:33:04}, priority = {2}, title = {Warp Processing: Dynamic Translation of Binaries to FPGA Circuits}, url = {http://dx.doi.org/10.1109/MC.2008.240}, volume = {41}, year = {2008} }

TY - JOUR ID - citeulike:3287556 L3 - citeulike-article-id:3287556 N2 - Warp processing dynamically and transparently transforms an executing microprocessor's binary kernels into customized field-programmable gate array (FPGA) circuits, commonly resulting in 2X to 100X speedup over executing on microprocessors. A new architecture and set of dynamic CAD tools demonstrate warp processing's potential. IS - 7 JF - Computer EP - 46 TI - Warp Processing: Dynamic Translation of Binaries to FPGA Circuits VL - 41 T2 - Computer SP - 40 KW - compiler_design KW - computer_architecture KW - fpga KW - reconfigurable_computing AU - Vahid, F AU - Stitt, G AU - Lysecky, R PY - 2008/// UR - http://dx.doi.org/10.1109/MC.2008.240 ER -