Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework Export

@article{citeulike:4154392, abstract = {<para> A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called <emphasis emphasistype="boldital"> geometric programming</emphasis> problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times. </para>}, author = {Liu, Q. and Constantinides, G. A. and Masselos, K. and Cheung, P. Y. K.}, booktitle = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, citeulike-article-id = {4154392}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TCAD.2009.2013541}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4785342}, doi = {10.1109/TCAD.2009.2013541}, journal = {Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, keywords = {compiler\_design, electronics\_design\_automation, fpga, high\_level\_synthesis}, number = {3}, pages = {305--315}, posted-at = {2009-03-09 09:48:34}, priority = {2}, title = {Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework}, url = {http://dx.doi.org/10.1109/TCAD.2009.2013541}, volume = {28}, year = {2009} }

TY - JOUR ID - citeulike:4154392 L3 - citeulike-article-id:4154392 N2 - <para> A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called <emphasis emphasistype="boldital"> geometric programming</emphasis> problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performance-optimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times. </para> IS - 3 JF - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on EP - 315 TI - Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework VL - 28 T2 - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on SP - 305 KW - compiler_design KW - electronics_design_automation KW - fpga KW - high_level_synthesis AU - Liu, Q AU - Constantinides, GA AU - Masselos, K AU - Cheung, PYK PY - 2009/// UR - http://dx.doi.org/10.1109/TCAD.2009.2013541 ER -