An FPGA-specific approach to floating-point accumulation and sum-of-products Export

@inproceedings{citeulike:5632658, abstract = {This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable to that of a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. A novel architecture is proposed that feeds the previous accumulator out of a floating-point multiplier whose rounding logic has been removed, again improving the area/accuracy tradeoff. These architectures are implemented within the FloPoCo generator, freely available under the LGPL.}, author = {de Dinechin, Florent and Pasca, B. and Cret, O. and Tudoran, R.}, booktitle = {ICECE Technology, 2008. FPT 2008. International Conference on}, citeulike-article-id = {5632658}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/FPT.2008.4762363}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4762363}, day = {27}, doi = {10.1109/FPT.2008.4762363}, journal = {ICECE Technology, 2008. FPT 2008. International Conference on}, keywords = {floating\_point, fpga}, month = {January}, pages = {33--40}, posted-at = {2009-11-06 16:33:09}, priority = {2}, title = {An FPGA-specific approach to floating-point accumulation and sum-of-products}, url = {http://dx.doi.org/10.1109/FPT.2008.4762363}, year = {2009} }

TY - CONF ID - citeulike:5632658 L3 - citeulike-article-id:5632658 N2 - This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable to that of a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. A novel architecture is proposed that feeds the previous accumulator out of a floating-point multiplier whose rounding logic has been removed, again improving the area/accuracy tradeoff. These architectures are implemented within the FloPoCo generator, freely available under the LGPL. JF - ICECE Technology, 2008. FPT 2008. International Conference on EP - 40 TI - An FPGA-specific approach to floating-point accumulation and sum-of-products T2 - ICECE Technology, 2008. FPT 2008. International Conference on SP - 33 KW - floating_point KW - fpga AU - de Dinechin, Florent AU - Pasca, B AU - Cret, O AU - Tudoran, R PY - 2009/01/27/ UR - http://dx.doi.org/10.1109/FPT.2008.4762363 ER -