On the design of IEEE compliant floating point units Export

@article{citeulike:6081028, abstract = {Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm}, author = {Even, G. and Paul, W. J.}, citeulike-article-id = {6081028}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/12.859536}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=859536}, day = {06}, doi = {10.1109/12.859536}, journal = {Computers, IEEE Transactions on}, keywords = {floating\_point, verification, vlsi\_design}, month = {August}, number = {5}, pages = {398--413}, posted-at = {2009-11-06 15:03:45}, priority = {2}, title = {On the design of IEEE compliant floating point units}, url = {http://dx.doi.org/10.1109/12.859536}, volume = {49}, year = {2002} }

TY - JOUR ID - citeulike:6081028 L3 - citeulike-article-id:6081028 N2 - Engineering design methodology recommends designing a system as follows: Start with an unambiguous specification, partition the system into blocks, specify the functionality of each block, design each block separately, and glue the blocks together. Verifying the correctness of an implementation then reduces to a local verification procedure. We apply this methodology for designing a provably correct IEEE rounding unit that can be used for various operations, such as addition and multiplication. First, we provide a mathematical and, hopefully, unambiguous definition of the IEEE Standard which specifies the functionality. We give explicit and concise rules for gluing the rounding unit with a floating-point adder and multiplier. We then present floating-point addition and multiplication algorithms that use the rounding unit. To the best of our knowledge, our design is the first publication that deals with detecting exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit in a floating point unit. Our abstraction level avoids bit-level representations and arguments to help clarify the functionality of the algorithm IS - 5 JF - Computers, IEEE Transactions on EP - 413 TI - On the design of IEEE compliant floating point units VL - 49 SP - 398 KW - floating_point KW - verification KW - vlsi_design AU - Even, G AU - Paul, WJ PY - 2002/08/06/ UR - http://dx.doi.org/10.1109/12.859536 ER -