A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency Export

@article{citeulike:6081035, abstract = {This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes Z = AB + CD + EF + GH in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The intermediate rounding is merged with shift alignment, and intermediate carry-propagated addition and normalization are omitted to reduce latency in the proposed architecture. The proposed DP4 unit is implemented with 0.18-mum CMOS technology and has 12.8-ns critical path delay, which is reduced by 45.5 percent compared to a previous DP4 implementation using discrete multipliers and adders. The proposed DP4 unit also reduces the cycle time of 3D graphics applications by 12.4 percent on the average compared to the usual 3D graphics FPU based on four-way multiply-add-fused units.}, author = {Kim, Donghyun and Kim, Lee-Sup}, citeulike-article-id = {6081035}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/TC.2008.210}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4674343}, day = {17}, doi = {10.1109/TC.2008.210}, journal = {Computers, IEEE Transactions on}, keywords = {floating\_point, linear\_algebra, vlsi\_design}, month = {November}, number = {7}, pages = {890--901}, posted-at = {2009-11-06 15:05:48}, priority = {2}, title = {A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency}, url = {http://dx.doi.org/10.1109/TC.2008.210}, volume = {58}, year = {2008} }

TY - JOUR ID - citeulike:6081035 L3 - citeulike-article-id:6081035 N2 - This paper presents the algorithm and implementation of a new high-performance functional unit for floating-point four-dimensional vector inner product (4D dot product; DP4), which is most frequently performed in 3D graphics application. The proposed IEEE-compliant DP4 unit computes Z = AB + CD + EF + GH in one path and keeps the intermediate rounding by IEEE-754 rounding to nearest even. The intermediate rounding is merged with shift alignment, and intermediate carry-propagated addition and normalization are omitted to reduce latency in the proposed architecture. The proposed DP4 unit is implemented with 0.18-mum CMOS technology and has 12.8-ns critical path delay, which is reduced by 45.5 percent compared to a previous DP4 implementation using discrete multipliers and adders. The proposed DP4 unit also reduces the cycle time of 3D graphics applications by 12.4 percent on the average compared to the usual 3D graphics FPU based on four-way multiply-add-fused units. IS - 7 JF - Computers, IEEE Transactions on EP - 901 TI - A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency VL - 58 SP - 890 KW - floating_point KW - linear_algebra KW - vlsi_design AU - Kim, Donghyun AU - Kim, Lee-Sup PY - 2008/11/17/ UR - http://dx.doi.org/10.1109/TC.2008.210 ER -