JHDL-an HDL for reconfigurable systems Export

@inproceedings{citeulike:620598, abstract = {JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard programming abstractions found in object-oriented languages. JHDL manages FPGA resources in a manner that is similar to the way object-oriented languages manage memory: circuits are treated as distinct objects and a circuit is configured onto a configurable computing machine (CCM) by invoking its constructor effectively ” constructing ” an instance of the circuit onto the reconfigurable platform just as object instances are allocated in memory with conventional object-oriented languages. This approach of using object constructors/destructors to control the circuit lifetime on a CCM is a powerful technique that naturally leads to a dual simulation/execution environment where a designer can easily switch between either software simulation or hardware execution on a CCM with a single application description. Moreover JHDL supports dual hardware/software execution; parts of the application described using JHDL circuit constructs can be executed on the CCM while the remainder of the application the-GUI for example-can run on the CCM host. Based on an existing programming language (Java), JHDL requires no language extensions and can be used with any standard Java 1.1 distribution}, author = {Bellows, P. and Hutchings, B.}, citeulike-article-id = {620598}, citeulike-linkout-0 = {http://dx.doi.org/10.1109/FPGA.1998.707895}, citeulike-linkout-1 = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=707895}, doi = {10.1109/FPGA.1998.707895}, journal = {FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on}, keywords = {hdl, hdl\_tool, language\_embedding, open\_source\_eda, reconfigurable\_platforms}, pages = {175--184}, posted-at = {2007-04-04 13:45:31}, priority = {2}, title = {JHDL-an HDL for reconfigurable systems}, url = {http://dx.doi.org/10.1109/FPGA.1998.707895}, year = {1998} }

TY - CONF ID - citeulike:620598 L3 - citeulike-article-id:620598 N2 - JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard programming abstractions found in object-oriented languages. JHDL manages FPGA resources in a manner that is similar to the way object-oriented languages manage memory: circuits are treated as distinct objects and a circuit is configured onto a configurable computing machine (CCM) by invoking its constructor effectively “constructing ” an instance of the circuit onto the reconfigurable platform just as object instances are allocated in memory with conventional object-oriented languages. This approach of using object constructors/destructors to control the circuit lifetime on a CCM is a powerful technique that naturally leads to a dual simulation/execution environment where a designer can easily switch between either software simulation or hardware execution on a CCM with a single application description. Moreover JHDL supports dual hardware/software execution; parts of the application described using JHDL circuit constructs can be executed on the CCM while the remainder of the application the-GUI for example-can run on the CCM host. Based on an existing programming language (Java), JHDL requires no language extensions and can be used with any standard Java 1.1 distribution JF - FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on EP - 184 TI - JHDL-an HDL for reconfigurable systems SP - 175 KW - hdl KW - hdl_tool KW - language_embedding KW - open_source_eda KW - reconfigurable_platforms AU - Bellows, P AU - Hutchings, B PY - 1998/// UR - http://dx.doi.org/10.1109/FPGA.1998.707895 ER -