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mmuecke's high_level_synthesis [64 articles]

Recent papers added to mmuecke's library classified by the tag high_level_synthesis. You can also see everyone's high_level_synthesis.
  • Using symbolic algebra in algorithmic level DSP synthesis
    (2001), pp. 277-282.
    by Armita Peymandoust, Giovanni De Micheli
    posted to term_rewriting high_level_synthesis by mmuecke on 2008-06-06 14:46:52 as **
  • Efficient design methods for embedded communication systems
    EURASIP J. Embedded Syst., Vol. 2006, No. 1. (January 2006), pp. 21-21.
    by M Holzer, B Knerr, P Belanovic, M Rupp
    posted to survey high_level_synthesis fixedpoint electronics_design_automation by mmuecke on 2008-06-05 17:39:37 as ** along with 1 person jhibbits
  • Trident: From High-Level Language to Hardware Circuitry
    Computer, Vol. 40, No. 3. (2007), pp. 28-37.
    by Justin L Tripp, Maya B Gokhale, Kristopher D Peterson
    posted to high_level_synthesis fpga electronics_design_automation by mmuecke on 2008-05-27 10:37:41 as ** along with 2 people hamish peskin
  • Sparse Matrix Computations on Reconfigurable Hardware
    Computer, Vol. 40, No. 3. (2007), pp. 58-64.
    by Viktor K Prasanna, Gerald R Morris
    posted to sparse_matrix reconfigurable_computing high-performance_computing high_level_synthesis floating_point by mmuecke on 2008-05-26 13:09:30 as ** along with 4 people hamish peskin smithmc esak
  • Programming paradigms for reconfigurable computing
    Microprocessors and Microsystems, Vol. 29, No. 10. (5 December 2005), pp. 435-450.
    by Gareth Lee, George Milne
    posted to hdl high_level_synthesis language_design reconfigurable_computing trends by mmuecke on 2008-04-17 21:02:13 as **
  • An FPGA-based VLIW processor with custom hardware execution
    (2005), pp. 107-117.
    by Alex K Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster
    posted to computer_architecture electronics_design_automation fpga high_level_synthesis reconfigurable_computing reconfigurable_platforms vhdl by mmuecke on 2008-04-10 09:46:03 as **
  • notes Vector processing as a soft-core CPU accelerator
    (2008), pp. 222-232.
    by Jason Yu, Guy Lemieux, Christpher Eagleston
    posted to electronics_design_automation fpga hdl_tool high_level_synthesis by mmuecke on 2008-03-17 16:04:35 as **
  • CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures
    (2008), pp. 261-261.
    by Andrew R Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan
    posted to electronics_design_automation fpga high_level_synthesis by mmuecke on 2008-03-17 15:56:25 as **
  • Productivity of High-Level Languages on Reconfigurable Computers: An HPC Perspective
    Field-Programmable Technology, 2007. ICFPT 2007. International Conference on (2007), pp. 257-260.
    by Esam El-Araby, Preetham Nosum, Tarek El-Ghazawi
    posted to electronics_design_automation hdl high_level_synthesis language_design parallel_programming reconfigurable_computing by mmuecke on 2008-02-07 07:06:34 as *****
  • A bitwidth-aware extension to the HDCaml Hardware Description Language
    (2006)
    by Manfred Muecke
    posted to confluence electronics_design_automation fixedpoint functional hdl high_level_synthesis language_design by mmuecke on 2008-01-23 14:25:45 as read
  • Word-length optimization for differentiable nonlinear systems
    ACM Trans. Des. Autom. Electron. Syst., Vol. 11, No. 1. (January 2006), pp. 26-43.
    by George A Constantinides
    posted to fixedpoint high_level_synthesis vlsi_design by mmuecke on 2008-01-18 15:40:10 as read
  • notes Abstraction Levels and Hardware Design
    EDA Design Line (July 2007)
    by John Sanguinetti
    posted to high_level_synthesis vlsi_design by mmuecke on 2008-01-15 09:48:09 as read
  • A Study of Design Efficiency with a High-Level Language for FPGAs
    Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International (2007), pp. 1-7.
    by Zain-Ul-Abdin, B Svensson
    posted to fpga hdl high_level_synthesis by mmuecke on 2007-11-27 00:24:49 as **
  • Synthesis And Optimization Of DSP Algorithms
    (2004)
    by George A Constantinides, Peter YK Cheung, Wayne Luk
    posted to book fixedpoint high_level_synthesis by mmuecke on 2007-10-15 11:30:04 as **
  • notes Stream-Oriented FPGA Computing in the Streams-C High Level Language
    (2000)
    by Maya B Gokhale, Janice M Stone, Jeff Arnold, Mirek Kalinowski
    posted to compiler_design hdl hdl_tool high_level_synthesis parallel_programming vhdl by mmuecke on 2007-10-04 22:40:08 as ****
  • Towards a general framework for FPGA based image processing using hardware skeletons
    Parallel Comput., Vol. 28, No. 7-8. (2002), pp. 1141-1154.
    by K Benkrid, D Crookes, A Benkrid
    posted to compiler_design fpga hdl hdl_tool high_level_synthesis image_processing parallel_programming by mmuecke on 2007-10-02 07:27:48 as *****
  • A reflective functional language for hardware design and theorem proving
    J. Funct. Program., Vol. 16, No. 2. (March 2006), pp. 157-196.
    by Jim Grundy, Tom Melham, John O'Leary
    posted to functional hdl high_level_synthesis by mmuecke on 2007-09-27 18:45:44 as *****
  • Hardware Synthesis from Term Rewriting Systems
    (2000), pp. 595-619.
    by James C Hoe, Arvind
    posted to formal_synthesis hdl hdl_tool high_level_synthesis by mmuecke on 2007-09-27 15:11:10 as *****
  • Memory Management for Synthesis of DSP Software
    (2006)
    by Praveen K Murthy, Shuvra S Bhattacharyya
    posted to high_level_synthesis by mmuecke on 2007-06-04 19:00:23 as **
  • notes Efficient FPGA hardware development: A multi-language approach
    J. Syst. Archit., Vol. 53, No. 4. (April 2007), pp. 184-209.
    by K Benkrid, A Benkrid, S Belkacemi
    posted to hdl high_level_synthesis by mmuecke on 2007-06-04 18:09:50 as *****
  • Data and memory optimization techniques for embedded systems
    ACM Trans. Des. Autom. Electron. Syst., Vol. 6, No. 2. (April 2001), pp. 149-206.
    by PR Panda, F Catthoor, ND Dutt, K Danckaert, E Brockmeyer, C Kulkarni, A Vandercappelle, PG Kjeldsberg
    posted to high_level_synthesis survey by mmuecke on 2007-06-04 18:04:44 as **
  • notes A methodology for generating verified combinatorial circuits
    (2004), pp. 249-258.
    by Oleg Kiselyov, Kedar N Swadi, Walid Taha
    posted to dsl hdl high_level_synthesis multi_stage_programming by mmuecke on 2007-06-04 17:52:32 as *****
  • Memory Access Optimization and RAM Inference for Pipeline Vectorization
    Field Programmable Logic and Applications (1999), pp. 61-70.
    by Markus Weinhardt, Wayne Luk
    posted to fpga hdl_tool high_level_synthesis by mmuecke on 2007-06-01 16:54:50 as **
  • From TLM to FPGA: rapid prototyping with SystemC and transaction level modeling
    Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on (2005), pp. 285-286.
    by W Klingauf, R Gunzel
    posted to high_level_synthesis hw_ip_reuse by mmuecke on 2007-05-29 15:15:39 as **
  • Occam on Field Programmable Gate Arrays - Fast Prototyping of Parallel Embedded Systems.
    (2000)
    by Roger MA Peel, Barry M Cook
    posted to high_level_synthesis parallel_programming by mmuecke on 2007-05-03 10:30:21 as **
  • Compiling Occam into field-programmable gate arrays
    (1991), pp. 271-283.
    by I Page, W Luk
    edited by W Moore, W Luk
    posted to high_level_synthesis parallel_programming by mmuecke on 2007-05-03 10:15:56 as **
  • Design of future systems
    (1998)
    by I Page
    posted to high_level_synthesis trends by mmuecke on 2007-05-03 10:13:18 as **
  • Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems
    Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on (2006), pp. 280-285.
    by Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau
    posted to fixedpoint high_level_synthesis by mmuecke on 2007-05-03 08:32:41 as **
  • FRIDGE: a fixed-point design and simulation environment
    Design, Automation and Test in Europe, 1998., Proceedings (1998), pp. 429-435.
    by H Keding, M Willems, M Coors, H Meyr
    posted to fixedpoint high_level_synthesis by mmuecke on 2007-05-02 16:31:20 as **
  • notes CHESS: a comprehensive tool for CDFG extraction and synthesis of low power designs from VHDL
    Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on, Vol. 00 (2006), 6 pp..
    by N Ranganathan, R Namballa, N Hanchate
    posted to dfg hdl_tool high_level_synthesis by mmuecke on 2007-05-02 15:48:50 as **
  • CHESS: A TOOL FOR CDFG EXTRACTION AND HIGH-LEVEL SYNTHESIS OF VLSI SYSTEMS
    (July 2003)
    by Ravi K Namballa
    posted to dfg hdl_tool high_level_synthesis vhdl by mmuecke on 2007-05-02 15:36:21 as **
  • notes Type systems equivalent to data-flow analyses for imperative languages
    Theor. Comput. Sci., Vol. 364, No. 3. (November 2006), pp. 292-310.
    by Peeter Laud, Tarmo Uustalu, Varmo Vene
    posted to dfg high_level_synthesis by mmuecke on 2007-04-27 14:44:21 as **
  • notes GAUT: An architectural synthesis tool for dedicated signal processors
    Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European (1993), pp. 14-19.
    by E Martin, O Sentieys, H Dubois, JL Philippe
    posted to dfg hdl_tool high_level_synthesis vhdl by mmuecke on 2007-04-27 14:14:16 as **
  • notes Taylor Expansion Diagrams (TED)
    by Qian Ren, Maciej Ciesielski, Serkan Askar, Jeremie Guillot, Emmanuel Boutillon
    posted to dfg high_level_synthesis by mmuecke on 2007-04-27 14:04:46 as **
  • Functional synthesis of digital systems with TASS
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 13, No. 5. (1994), pp. 537-552.
    by S Amellal, B Kaminska
    posted to dfg high_level_synthesis vhdl by mmuecke on 2007-04-26 15:00:59 as **
  • From VHDL to efficient and first-time-right designs: a formal approach
    ACM Trans. Des. Autom. Electron. Syst., Vol. 1, No. 2. (April 1996), pp. 205-250.
    by Peter FA Middelhoek, Sreeranga P Rajan
    posted to dfg high_level_synthesis image_processing vhdl by mmuecke on 2007-04-26 14:46:47 as read
  • notes Parallel algorithms development for programmable logic devices
    Adv. Eng. Softw., Vol. 37, No. 9. (September 2006), pp. 561-582.
    by Issam W Damaj
    posted to fpga functional high_level_synthesis parallel_algorithms parallel_programming by mmuecke on 2007-04-13 09:02:52 as **
  • Gropius - Advanced Reuse Concepts in a New Hardware Description Language
    by Dirk Eisenbiegler, Christian Blumenröhr
    posted to formal_language_theory formal_synthesis hdl high_level_synthesis by mmuecke on 2007-04-12 15:43:10 as **
  • notes Ein Kalkül für die Formale Schaltungssynthese
    (1999)
    by Dirk Eisenbiegler
    posted to formal_synthesis hdl high_level_synthesis by mmuecke on 2007-04-12 15:34:58 as **
  • notes High-Level Synthesis - Introduction to chip and system design
    (1992)
    by Daniel Gajski, Nikil Dutt, Allen Wu, Steve Lin
    posted to high_level_synthesis by mmuecke on 2007-04-12 08:16:25 as **
  • Defining an Enhanced RTL Semantics
    (2005), pp. 548-553.
    by Shuqing Zhao, Daniel D Gajski
    posted to hdl high_level_synthesis by mmuecke on 2007-04-10 14:06:43 as **
  • notes Design space exploration using arithmetic-level hardware--software cosimulation for configurable multiprocessor platforms
    Trans. on Embedded Computing Sys., Vol. 5, No. 2. (May 2006), pp. 355-382.
    by Jingzhao Ou, Viktor K Prasanna
    posted to fixedpoint high_level_synthesis sopc by mmuecke on 2007-04-10 09:39:16 as **
  • Sassy: A Language and Optimizing Compiler for Image Processing on Reconfigurable Computing Systems
    : Computer Vision Systems: First International Conference, ICVS'99, Las Palmas, Gran Canaria, Spain, January 1999. Proceedings (1999), 83.
    by Jeffrey P Hammes, Bruce A Draper, Willem AP Böhm
    posted to hdl high_level_synthesis image_processing by mmuecke on 2007-04-04 15:53:18 as **
  • Synthesis of hardware models in C with pointers and complex data structures
    IEEE Trans. Very Large Scale Integr. Syst., Vol. 9, No. 6. (December 2001), pp. 743-756.
    by Luc Séméria, Koichi Sato, Giovanni De Micheli
    posted to dfg high_level_synthesis by mmuecke on 2007-04-03 13:21:16 as **
  • Handel-C Language Reference Manual
    (2004)
    by Celoxica
    posted to hdl high_level_synthesis by mmuecke on 2007-03-30 17:17:21 as **
  • notes SystemC Synthesizable Subset Draft 1.1.18
    (December 2004)
    edited by "synthesis
    posted to hdl high_level_synthesis systemc by mmuecke on 2007-03-30 13:17:46 as **
  • notes Flow graph representation
    (1986), pp. 503-509.
    by Alex Orailoglu, Daniel D Gajski
    posted to dfg hdl hdl_tool high_level_synthesis survey by mmuecke on 2007-03-29 14:39:08 as **
  • notes Bridging the domains of high-level and logic synthesis
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 21, No. 5. (2002), pp. 582-596.
    by RA Bergamaschi
    posted to dfg hdl high_level_synthesis survey vhdl by mmuecke on 2007-03-28 13:51:13 as **
  • A hierarchical CDFG as intermediate representation for hardware/software codesign
    Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on, Vol. 2 (2002), pp. 1429-1432 vol.2.
    by Qiang Wu, Yunfeng Wang, Jinian Bian, Weimin Wu, Hongxi Xue
    posted to dfg high_level_synthesis by mmuecke on 2007-03-24 17:27:49 as **
  • notes Task graph extraction for embedded system synthesis
    VLSI Design, 2003. Proceedings. 16th International Conference on (2003), pp. 480-486.
    by KS Vallerio, NK Jha
    posted to dfg high_level_synthesis by mmuecke on 2007-03-23 15:31:14 as read
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